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Message-ID: <e923418a99e44cd38483ea24e4c1d373@huawei.com>
Date: Thu, 9 Mar 2023 18:24:29 +0000
From: Shameerali Kolothum Thodi <shameerali.kolothum.thodi@...wei.com>
To: Robin Murphy <robin.murphy@....com>,
Nicolin Chen <nicolinc@...dia.com>,
"jgg@...dia.com" <jgg@...dia.com>,
"will@...nel.org" <will@...nel.org>
CC: "eric.auger@...hat.com" <eric.auger@...hat.com>,
"kevin.tian@...el.com" <kevin.tian@...el.com>,
"baolu.lu@...ux.intel.com" <baolu.lu@...ux.intel.com>,
"joro@...tes.org" <joro@...tes.org>,
"jean-philippe@...aro.org" <jean-philippe@...aro.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"iommu@...ts.linux.dev" <iommu@...ts.linux.dev>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH v1 06/14] iommu/arm-smmu-v3: Unset corresponding STE
fields when s2_cfg is NULL
> -----Original Message-----
> From: Robin Murphy [mailto:robin.murphy@....com]
> Sent: 09 March 2023 13:13
> To: Nicolin Chen <nicolinc@...dia.com>; jgg@...dia.com; will@...nel.org
> Cc: eric.auger@...hat.com; kevin.tian@...el.com; baolu.lu@...ux.intel.com;
> joro@...tes.org; Shameerali Kolothum Thodi
> <shameerali.kolothum.thodi@...wei.com>; jean-philippe@...aro.org;
> linux-arm-kernel@...ts.infradead.org; iommu@...ts.linux.dev;
> linux-kernel@...r.kernel.org
> Subject: Re: [PATCH v1 06/14] iommu/arm-smmu-v3: Unset corresponding
> STE fields when s2_cfg is NULL
>
> On 2023-03-09 10:53, Nicolin Chen wrote:
> > From: Eric Auger <eric.auger@...hat.com>
> >
> > Despite the spec does not seem to mention this, on some implementations,
> > when the STE configuration switches from an S1+S2 cfg to an S1 only one,
> > a C_BAD_STE error would happen if dst[3] (S2TTB) is not reset.
>
> Can you provide more details, since it's not clear whether this is a
> hardware erratum workaround or a bodge around the driver itself doing
> something wrong like not doing a proper break-before-make transition of
> the STE. The architecture explicitly states that all the STE.S2* fields
> except S2VMID and potentially S2S are ignored when Stage 2 is bypassed.
Took a while to locate the email thread where this was discussed,
https://patchwork.kernel.org/cover/11449895/#23244457
This was observed on a HiSilicon implementation where, if the SMMUv3 is configured with
both Stage 1 and Stage 2 (nested) mode once, then it is not possible to configure it back
for Stage 1 mode for the same device(stream id).
IIRC, the SMMUv3 implementation on these boards expects to set the S2TTB field in STE to zero
when using S1, otherwise it reports C_BAD_STE error. :(
You are right that the specification doesn't demand this and I am not sure there are any other
Hardware that requires this.
Could we please have this with a comment added in the code?
Thanks,
Shameer
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