linux-kernel - Re: [PATCH v5 10/19] clk: mediatek: Add MT8188 mfgcfg clock support

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Message-ID: <3a4ab2f1da5f3d8a8bf6d2f4e3574d3a2708e229.camel@mediatek.com>
Date:   Thu, 9 Mar 2023 05:30:41 +0000
From:   Garmin Chang (張家銘) 
        <Garmin.Chang@...iatek.com>
To:     "wenst@...omium.org" <wenst@...omium.org>
CC:     "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "mturquette@...libre.com" <mturquette@...libre.com>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "sboyd@...nel.org" <sboyd@...nel.org>,
        "linux-mediatek@...ts.infradead.org" 
        <linux-mediatek@...ts.infradead.org>,
        Project_Global_Chrome_Upstream_Group 
        <Project_Global_Chrome_Upstream_Group@...iatek.com>,
        "richardcochran@...il.com" <richardcochran@...il.com>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "krzysztof.kozlowski+dt@...aro.org" 
        <krzysztof.kozlowski+dt@...aro.org>,
        "matthias.bgg@...il.com" <matthias.bgg@...il.com>,
        "linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>
Subject: Re: [PATCH v5 10/19] clk: mediatek: Add MT8188 mfgcfg clock support

On Fri, 2023-02-03 at 15:02 +0800, Chen-Yu Tsai wrote:
> On Thu, Jan 19, 2023 at 8:50 PM Garmin.Chang <
> Garmin.Chang@...iatek.com> wrote:
> > 
> > Add MT8188 mfg clock controller which provides clock gate
> > control for GPU.
> > 
> > Signed-off-by: Garmin.Chang <Garmin.Chang@...iatek.com>
> > ---
> >  drivers/clk/mediatek/Makefile         |  2 +-
> >  drivers/clk/mediatek/clk-mt8188-mfg.c | 47
> > +++++++++++++++++++++++++++
> >  2 files changed, 48 insertions(+), 1 deletion(-)
> >  create mode 100644 drivers/clk/mediatek/clk-mt8188-mfg.c
> > 
> > diff --git a/drivers/clk/mediatek/Makefile
> > b/drivers/clk/mediatek/Makefile
> > index 4a599122f761..a0fd87a882b5 100644
> > --- a/drivers/clk/mediatek/Makefile
> > +++ b/drivers/clk/mediatek/Makefile
> > @@ -86,7 +86,7 @@ obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-
> > mcu.o clk-mt8186-topckgen.o clk-mt
> >  obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-
> > mt8188-topckgen.o \
> >                                    clk-mt8188-peri_ao.o clk-mt8188-
> > infra_ao.o \
> >                                    clk-mt8188-cam.o clk-mt8188-
> > ccu.o clk-mt8188-img.o \
> > -                                  clk-mt8188-ipe.o
> > +                                  clk-mt8188-ipe.o clk-mt8188-
> > mfg.o
> >  obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
> >  obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
> >  obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> > diff --git a/drivers/clk/mediatek/clk-mt8188-mfg.c
> > b/drivers/clk/mediatek/clk-mt8188-mfg.c
> > new file mode 100644
> > index 000000000000..57b0afb5f4df
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt8188-mfg.c
> > @@ -0,0 +1,47 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +//
> > +// Copyright (c) 2022 MediaTek Inc.
> > +// Author: Garmin Chang <garmin.chang@...iatek.com>
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/platform_device.h>
> > +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> > +
> > +#include "clk-gate.h"
> > +#include "clk-mtk.h"
> > +
> > +static const struct mtk_gate_regs mfgcfg_cg_regs = {
> > +       .set_ofs = 0x4,
> > +       .clr_ofs = 0x8,
> > +       .sta_ofs = 0x0,
> > +};
> > +
> > +#define GATE_MFG(_id, _name, _parent,
> > _shift)                          \
> > +       GATE_MTK_FLAGS(_id, _name, _parent, &mfgcfg_cg_regs,
> > _shift,    \
> > +                      &mtk_clk_gate_ops_setclr,
> > CLK_SET_RATE_PARENT)
> > +
> > +static const struct mtk_gate mfgcfg_clks[] = {
> > +       GATE_MFG(CLK_MFGCFG_BG3D, "mfgcfg_bg3d",
> > "top_mfg_core_tmp", 0),
> 
> Are you sure the parent isn't "mfg_ck_fast_ref"?

Thank you for your suggestions. 
OK, I will chnage to mfg_ck_fast_ref in v6.

> 
> ChenYu