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Message-ID: <37adba14-1add-187c-01b5-5109be38018e@collabora.com>
Date:   Fri, 10 Mar 2023 09:53:16 +0000
From:   Lucas Tanure <lucas.tanure@...labora.com>
To:     Marc Zyngier <maz@...nel.org>
Cc:     Vinod Koul <vkoul@...nel.org>,
        Kishon Vijay Abraham I <kishon@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Heiko Stuebner <heiko@...ech.de>,
        Thomas Gleixner <tglx@...utronix.de>,
        Lorenzo Pieralisi <lpieralisi@...nel.org>,
        Krzysztof Wilczynski <kw@...ux.com>,
        Bjorn Helgaas <bhelgaas@...gle.com>, Qu Wenruo <wqu@...e.com>,
        Piotr Oniszczuk <piotr.oniszczuk@...il.com>,
        Peter Geis <pgwipeout@...il.com>,
        Kever Yang <kever.yang@...k-chips.com>,
        linux-phy@...ts.infradead.org, devicetree@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org,
        linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org,
        linux-pci@...r.kernel.org, kernel@...labora.com,
        Robin Murphy <robin.murphy@....com>
Subject: Re: [PATCH 1/7] irqchip/gic-v3: Add a DMA Non-Coherent flag

On 10-03-2023 08:56, Marc Zyngier wrote:
> On 2023-03-10 08:05, Lucas Tanure wrote:
>> The GIC600 integration in RK356x, used in rk3588, doesn't support
>> any of the shareability or cacheability attributes, and requires
>> both values to be set to 0b00 for all the ITS and Redistributor
>> tables.
>>
>> This is loosely based on prior work from XiaoDong Huang and
>> Peter Geis fixing this issue specifically for Rockchip 356x.
> 
> No.
> 
> If we are going to do *anything* about this thing, it is by
> describing the actual topology.
What do you mean by describe the topology?
What kind of information are you expecting?


And it has to work for both DT
> and ACPI.
> 
> Alternatively, this is an erratum.
> 
>          M.

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