linux-kernel - Re: [PATCH] LoongArch: Make WriteCombine configurable for ioremap()

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <939c8d17-6166-0c9b-6c58-6d49fd89841f@xen0n.name>
Date:   Tue, 14 Mar 2023 18:11:56 +0800
From:   WANG Xuerui <kernel@...0n.name>
To:     Huacai Chen <chenhuacai@...nel.org>, Xi Ruoyao <xry111@...111.site>
Cc:     Huacai Chen <chenhuacai@...ngson.cn>, loongarch@...ts.linux.dev,
        Xuefeng Li <lixuefeng@...ngson.cn>,
        Guo Ren <guoren@...nel.org>,
        Jiaxun Yang <jiaxun.yang@...goat.com>,
        linux-kernel@...r.kernel.org, loongson-kernel@...ts.loongnix.cn
Subject: Re: [PATCH] LoongArch: Make WriteCombine configurable for ioremap()

On 2023/3/14 18:02, Huacai Chen wrote:
> Hi, Ruoyao,
> 
> On Tue, Mar 14, 2023 at 5:41 PM Xi Ruoyao <xry111@...111.site> wrote:
>>
>> On Tue, 2023-03-14 at 16:54 +0800, Huacai Chen wrote:
>>> LoongArch maintains cache coherency in hardware, but when works with
>>> LS7A chipsets the WUC attribute (Weak-ordered UnCached, which is similar
>>> to WriteCombine) is out of the scope of cache coherency machanism for
>>> PCIe devices (this is a PCIe protocol violation, may be fixed in newer
>>> chipsets).
>>
>> IIUC all launched LS7A models (7A1000 and 7A2000) suffers this issue?
> Yes, very unfortunately, but this issue is only observed in the amdgpu
> driver now.

It's PCIe protocol violation after all, and we can never be sure about 
the vast amount of hardware untested on loongarch after all. Miserable 
as the performance hit may get, we don't really have another choice, 
unfortunately. Someone needs to lecture the LS7A team real hard!

>>
>>> This means WUC can only used for write-only memory regions now, so this
>>> option is disabled by default (means WUC falls back to SUC for ioremap).
>>> You can enable this option if the kernel is ensured to run on bug-free
>>> hardwares.
>>
>> Hmm, is it possible to make a PCI quirk so SUC/WUC will be decided
>> automatically from the vendor:device ID of the PCI root controller?
>> Then we don't need to rely on the user or distro maintainer to select an
>> option.  I see there is already many architecture-dependant #if
>> directives in drivers/pci/quirks.c so I guess such a quirk is acceptable
>> in PCI tree...
> Not a good idea, pci quirks need too long a time to review, and we
> don't know when this issue can be fixed in hardware.
> 
>>
>> If a PCI quirk is not possible, then is it possible to make a kernel
>> command line option, leaving this CONFIG as the default value of the
>> option?  I guess in the future many LoongArch users will just install a
>> binary distro, then it would be much easier to edit grub.cfg than
>> rebuilding the kernel when they finally buy a compliant PCIe controller.
> If we use command line parameter, we can remove this Kconfig option.

An option is still useful as specifying the compile-time default for 
such a kernel parameter, IMO.

-- 
WANG "xen0n" Xuerui

Linux/LoongArch mailing list: https://lore.kernel.org/loongarch/