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Message-ID: <26c4712672de6c4f70f88c6846bc892f.sboyd@kernel.org>
Date: Tue, 21 Mar 2023 16:42:05 -0700
From: Stephen Boyd <sboyd@...nel.org>
To: Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Michael Turquette <mturquette@...libre.com>,
Rob Herring <robh+dt@...nel.org>,
Yinbo Zhu <zhuyinbo@...ngson.cn>, devicetree@...r.kernel.org,
linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org
Cc: Jianmin Lv <lvjianmin@...ngson.cn>, wanghongliang@...ngson.cn,
Liu Peibao <liupeibao@...ngson.cn>,
loongson-kernel@...ts.loongnix.cn, Yinbo Zhu <zhuyinbo@...ngson.cn>
Subject: Re: [PATCH v15 2/2] clk: clk-loongson2: add clock controller driver support
Quoting Yinbo Zhu (2023-03-21 06:07:10)
> diff --git a/drivers/clk/clk-loongson2.c b/drivers/clk/clk-loongson2.c
> new file mode 100644
> index 000000000000..090810655511
> --- /dev/null
> +++ b/drivers/clk/clk-loongson2.c
> @@ -0,0 +1,344 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Author: Yinbo Zhu <zhuyinbo@...ngson.cn>
> + * Copyright (C) 2022-2023 Loongson Technology Corporation Limited
> + */
> +
> +#include <linux/err.h>
> +#include <linux/init.h>
> +#include <linux/clk-provider.h>
> +#include <linux/slab.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/io-64-nonatomic-lo-hi.h>
> +#include <dt-bindings/clock/loongson,ls2k-clk.h>
> +
> +#define LOONGSON2_PLL_MULT_SHIFT 32
> +#define LOONGSON2_PLL_MULT_WIDTH 10
> +#define LOONGSON2_PLL_DIV_SHIFT 26
> +#define LOONGSON2_PLL_DIV_WIDTH 6
> +#define LOONGSON2_APB_FREQSCALE_SHIFT 20
> +#define LOONGSON2_APB_FREQSCALE_WIDTH 3
> +#define LOONGSON2_USB_FREQSCALE_SHIFT 16
> +#define LOONGSON2_USB_FREQSCALE_WIDTH 3
> +#define LOONGSON2_SATA_FREQSCALE_SHIFT 12
> +#define LOONGSON2_SATA_FREQSCALE_WIDTH 3
> +#define LOONGSON2_BOOT_FREQSCALE_SHIFT 8
> +#define LOONGSON2_BOOT_FREQSCALE_WIDTH 3
> +
> +static void __iomem *loongson2_pll_base;
Why is this a global?
> +
> +static const struct clk_parent_data pdata[] = {
> + { .fw_name = "ref_100m",},
> +};
> +
> +static struct clk_hw *loongson2_clk_register(struct device *dev,
> + const char *name,
> + const char *parent_name,
> + const struct clk_ops *ops,
> + unsigned long flags)
> +{
> + int ret;
> + struct clk_hw *hw;
> + struct clk_init_data init;
> +
> + /* allocate the divider */
Remove useless comment.
> + hw = devm_kzalloc(dev, sizeof(*hw), GFP_KERNEL);
> + if (!hw)
> + return ERR_PTR(-ENOMEM);
> +
> + init.name = name;
> + init.ops = ops;
> + init.flags = flags;
> + init.num_parents = 1;
> +
> + if (!parent_name)
> + init.parent_data = pdata;
> + else
> + init.parent_names = &parent_name;
> +
> + hw->init = &init;
> +
> + /* register the clock */
Remove useless comment.
> + ret = devm_clk_hw_register(dev, hw);
> + if (ret)
> + hw = ERR_PTR(ret);
> +
> + return hw;
> +}
> +
[....]
> +
> +static const struct clk_ops loongson2_sata_clk_ops = {
> + .recalc_rate = loongson2_sata_recalc_rate,
> +};
> +
> +static inline void loongson2_check_clk_hws(struct clk_hw *clks[], unsigned int count)
This needs to return an error instead of be void.
> +{
> + unsigned int i;
> +
> + for (i = 0; i < count; i++)
> + if (IS_ERR(clks[i]))
> + pr_err("Loongson2 clk %u: register failed with %ld\n",
> + i, PTR_ERR(clks[i]));
> +}
> +
> +static inline void loongson2_clocks_init(struct device *dev)
> +{
> + struct clk_hw **hws;
> + struct clk_hw_onecell_data *clk_hw_data;
> + spinlock_t loongson2_clk_lock;
> +
> + clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, LOONGSON2_CLK_END),
> + GFP_KERNEL);
> + if (WARN_ON(!clk_hw_data))
> + return;
> +
> + clk_hw_data->num = LOONGSON2_CLK_END;
> + hws = clk_hw_data->hws;
> +
> + hws[LOONGSON2_NODE_PLL] = loongson2_clk_register(dev, "node_pll",
> + NULL,
> + &loongson2_node_clk_ops, 0);
> +
> + hws[LOONGSON2_DDR_PLL] = loongson2_clk_register(dev, "ddr_pll",
> + NULL,
> + &loongson2_ddr_clk_ops, 0);
> +
> + hws[LOONGSON2_DC_PLL] = loongson2_clk_register(dev, "dc_pll",
> + NULL,
> + &loongson2_dc_clk_ops, 0);
> +
> + hws[LOONGSON2_PIX0_PLL] = loongson2_clk_register(dev, "pix0_pll",
> + NULL,
> + &loongson2_pix0_clk_ops, 0);
> +
> + hws[LOONGSON2_PIX1_PLL] = loongson2_clk_register(dev, "pix1_pll",
> + NULL,
> + &loongson2_pix1_clk_ops, 0);
> +
> + hws[LOONGSON2_BOOT_CLK] = loongson2_clk_register(dev, "boot",
> + NULL,
> + &loongson2_boot_clk_ops, 0);
> +
> + hws[LOONGSON2_NODE_CLK] = clk_hw_register_divider(NULL, "node",
These should be devm_ variants so they're undone on failure.
> + "node_pll", 0,
> + loongson2_pll_base + 0x8, 0,
> + 6, CLK_DIVIDER_ONE_BASED,
> + &loongson2_clk_lock);
> +
> + /*
> + * The hda clk divisor in the upper 32bits and the clk-prodiver
> + * layer code doesn't support 64bit io operation thus a conversion
> + * is required that subtract shift by 32 and add 4byte to the hda
> + * address
> + */
> + hws[LOONGSON2_HDA_CLK] = clk_hw_register_divider(NULL, "hda",
> + "ddr_pll", 0,
> + loongson2_pll_base + 0x22, 12,
> + 7, CLK_DIVIDER_ONE_BASED,
> + &loongson2_clk_lock);
> +
> + hws[LOONGSON2_GPU_CLK] = clk_hw_register_divider(NULL, "gpu",
> + "ddr_pll", 0,
> + loongson2_pll_base + 0x18, 22,
> + 6, CLK_DIVIDER_ONE_BASED,
> + &loongson2_clk_lock);
> +
> + hws[LOONGSON2_DDR_CLK] = clk_hw_register_divider(NULL, "ddr",
> + "ddr_pll", 0,
> + loongson2_pll_base + 0x18, 0,
> + 6, CLK_DIVIDER_ONE_BASED,
> + &loongson2_clk_lock);
> +
> + hws[LOONGSON2_GMAC_CLK] = clk_hw_register_divider(NULL, "gmac",
> + "dc_pll", 0,
> + loongson2_pll_base + 0x28, 22,
> + 6, CLK_DIVIDER_ONE_BASED,
> + &loongson2_clk_lock);
> +
> + hws[LOONGSON2_DC_CLK] = clk_hw_register_divider(NULL, "dc",
> + "dc_pll", 0,
> + loongson2_pll_base + 0x28, 0,
> + 6, CLK_DIVIDER_ONE_BASED,
> + &loongson2_clk_lock);
> +
> + hws[LOONGSON2_APB_CLK] = loongson2_clk_register(dev, "apb",
> + "gmac",
> + &loongson2_apb_clk_ops, 0);
> +
> + hws[LOONGSON2_USB_CLK] = loongson2_clk_register(dev, "usb",
> + "gmac",
> + &loongson2_usb_clk_ops, 0);
> +
> + hws[LOONGSON2_SATA_CLK] = loongson2_clk_register(dev, "sata",
> + "gmac",
> + &loongson2_sata_clk_ops, 0);
> +
> + hws[LOONGSON2_PIX0_CLK] = clk_hw_register_divider(NULL, "pix0",
> + "pix0_pll", 0,
> + loongson2_pll_base + 0x38, 0, 6,
> + CLK_DIVIDER_ONE_BASED,
> + &loongson2_clk_lock);
> +
> + hws[LOONGSON2_PIX1_CLK] = clk_hw_register_divider(NULL, "pix1",
> + "pix1_pll", 0,
> + loongson2_pll_base + 0x48, 0, 6,
> + CLK_DIVIDER_ONE_BASED,
> + &loongson2_clk_lock);
> +
> + loongson2_check_clk_hws(hws, LOONGSON2_CLK_END);
> +
> + devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_hw_data);
Return this error code.
> +}
> +
> +static const struct of_device_id loongson2_clk_match_table[] = {
> + { .compatible = "loongson,ls2k-clk" },
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, loongson2_clk_match_table);
This table can go next to the driver instead of be above probe.
> +
> +static int loongson2_clk_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> +
> + loongson2_pll_base = devm_platform_ioremap_resource(pdev, 0);
> + if (!loongson2_pll_base)
Should be IS_ERR(loongson2_pll_base)
> + return PTR_ERR(loongson2_pll_base);
> +
> + loongson2_clocks_init(dev);
Please inline this function here.
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