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Message-ID: <62b766cef78d95793af95f428693c359.sboyd@kernel.org>
Date: Tue, 21 Mar 2023 16:57:52 -0700
From: Stephen Boyd <sboyd@...nel.org>
To: Conor Dooley <conor@...nel.org>,
Hal Feng <hal.feng@...rfivetech.com>, kernel@...il.dk
Cc: linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
linux-riscv@...ts.infradead.org,
Michael Turquette <mturquette@...libre.com>,
Philipp Zabel <p.zabel@...gutronix.de>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Albert Ou <aou@...s.berkeley.edu>,
Ben Dooks <ben.dooks@...ive.com>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Thomas Gleixner <tglx@...utronix.de>,
Marc Zyngier <maz@...nel.org>,
Emil Renner Berthing <emil.renner.berthing@...onical.com>,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v6 00/21] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC
Quoting Conor Dooley (2023-03-21 16:03:54)
>
> If you're happy on the driver side of things, do you want to pick those
> patches up on top of the bindings and send a PR to Stephen?
This sounds fine to me. Let me know if you plan to send a PR with the
starfive clk bits.
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