[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20230324074455.bosmaxwkbo7mlyvj@mobilestation>
Date: Fri, 24 Mar 2023 10:44:55 +0300
From: Serge Semin <fancer.lancer@...il.com>
To: Vinod Koul <vkoul@...nel.org>
Cc: Cai Huoqing <cai.huoqing@...ux.dev>,
Gustavo Pimentel <gustavo.pimentel@...opsys.com>,
Jingoo Han <jingoohan1@...il.com>,
Lorenzo Pieralisi <lpieralisi@...nel.org>,
Krzysztof WilczyĆski <kw@...ux.com>,
Rob Herring <robh@...nel.org>,
Bjorn Helgaas <bhelgaas@...gle.com>,
linux-kernel@...r.kernel.org, dmaengine@...r.kernel.org,
linux-pci@...r.kernel.org
Subject: Re: [PATCH v9 0/4] dmaengine: dw-edma: Add support for native HDMA
Hi Vinod
On Fri, Mar 24, 2023 at 10:14:14AM +0800, Cai Huoqing wrote:
> Add support for HDMA NATIVE, as long the IP design has set
> the compatible register map parameter-HDMA_NATIVE,
> which allows compatibility for native HDMA register configuration.
>
> The HDMA Hyper-DMA IP is an enhancement of the eDMA embedded-DMA IP.
> And the native HDMA registers are different from eDMA,
> so this patch add support for HDMA NATIVE mode.
>
> HDMA write and read channels operate independently to maximize
> the performance of the HDMA read and write data transfer over
> the link When you configure the HDMA with multiple read channels,
> then it uses a round robin (RR) arbitration scheme to select
> the next read channel to be serviced.The same applies when
> youhave multiple write channels.
>
> The native HDMA driver also supports a maximum of 16 independent
> channels (8 write + 8 read), which can run simultaneously.
> Both SAR (Source Address Register) and DAR (Destination Address Register)
> are aligned to byte.
>
> Cai Huoqing (1):
> dmaengine: dw-edma: Add support for native HDMA
>
> Cai huoqing (3):
> dmaengine: dw-edma: Rename dw_edma_core_ops structure to
> dw_edma_plat_ops
> dmaengine: dw-edma: Create a new dw_edma_core_ops structure to
> abstract controller operation
> dmaengine: dw-edma: Add HDMA DebugFS support
>
> Tested-by: Serge Semin <fancer.lancer@...il.com>
I finished the patchset review and testing. Could you have a look at
the series. If you are ok with what it does please merge in.
-Serge(y)
>
> v8->v9:
> [3/4]
> 1.Drop an empty line.
> [4/4]
> 2.Update commit log.
> 3.Remove unused macro
>
> v8 link:
> https://lore.kernel.org/lkml/20230323034944.78357-1-cai.huoqing@linux.dev/
>
> drivers/dma/dw-edma/Makefile | 8 +-
> drivers/dma/dw-edma/dw-edma-core.c | 86 ++----
> drivers/dma/dw-edma/dw-edma-core.h | 58 ++++
> drivers/dma/dw-edma/dw-edma-pcie.c | 4 +-
> drivers/dma/dw-edma/dw-edma-v0-core.c | 85 +++++-
> drivers/dma/dw-edma/dw-edma-v0-core.h | 14 +-
> drivers/dma/dw-edma/dw-hdma-v0-core.c | 296 +++++++++++++++++++
> drivers/dma/dw-edma/dw-hdma-v0-core.h | 17 ++
> drivers/dma/dw-edma/dw-hdma-v0-debugfs.c | 170 +++++++++++
> drivers/dma/dw-edma/dw-hdma-v0-debugfs.h | 22 ++
> drivers/dma/dw-edma/dw-hdma-v0-regs.h | 129 ++++++++
> drivers/pci/controller/dwc/pcie-designware.c | 2 +-
> include/linux/dma/edma.h | 7 +-
> 13 files changed, 807 insertions(+), 91 deletions(-)
> create mode 100644 drivers/dma/dw-edma/dw-hdma-v0-core.c
> create mode 100644 drivers/dma/dw-edma/dw-hdma-v0-core.h
> create mode 100644 drivers/dma/dw-edma/dw-hdma-v0-debugfs.c
> create mode 100644 drivers/dma/dw-edma/dw-hdma-v0-debugfs.h
> create mode 100644 drivers/dma/dw-edma/dw-hdma-v0-regs.h
>
> --
> 2.34.1
>
Powered by blists - more mailing lists