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Message-ID: <CAFC43E6-97E9-4E89-AABB-78E31037048A@alien8.de>
Date: Thu, 30 Mar 2023 19:05:58 +0200
From: Borislav Petkov <bp@...en8.de>
To: Thomas Gleixner <tglx@...utronix.de>,
Usama Arif <usama.arif@...edance.com>, dwmw2@...radead.org,
kim.phillips@....com, brgerst@...il.com
CC: piotrgorski@...hyos.org, oleksandr@...alenko.name,
arjan@...ux.intel.com, mingo@...hat.com,
dave.hansen@...ux.intel.com, hpa@...or.com, x86@...nel.org,
pbonzini@...hat.com, paulmck@...nel.org,
linux-kernel@...r.kernel.org, kvm@...r.kernel.org,
rcu@...r.kernel.org, mimoja@...oja.de, hewenliang4@...wei.com,
thomas.lendacky@....com, seanjc@...gle.com, pmenzel@...gen.mpg.de,
fam.zheng@...edance.com, punit.agrawal@...edance.com,
simon.evans@...edance.com, liangma@...ngbit.com,
gpiccoli@...lia.com, David Woodhouse <dwmw@...zon.co.uk>
Subject: Re: [PATCH v17 6/8] x86/smpboot: Send INIT/SIPI/SIPI to secondary CPUs in parallel
On March 30, 2023 6:46:24 PM GMT+02:00, Thomas Gleixner <tglx@...utronix.de> wrote:
>So that violates the rules of microcode loading that the sibling must be
>in a state where it does not execute anything which might be affected by
>the microcode update. The fragile startup code does not really qualify
>as such a state :)
Yeah I don't think we ever enforced this for early loading. The thread sync thing came with the late loading dance....
--
Sent from a small device: formatting sucks and brevity is inevitable.
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