linux-kernel - Re: gic700 shareability question

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Mon, 03 Apr 2023 09:08:13 +0100
From:   Marc Zyngier <maz@...nel.org>
To:     Peng Fan <peng.fan@....com>
Cc:     Lorenzo Pieralisi <lpieralisi@...nel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: gic700 shareability question

On Mon, 03 Apr 2023 02:36:31 +0100,
Peng Fan <peng.fan@....com> wrote:
> 
> Hi Marc,
> 
> > Subject: Re: gic700 shareability question
> > 
> > + Lorenzo
> > 
> > On Tue, 28 Mar 2023 13:48:19 +0100,
> > Peng Fan <peng.fan@....com> wrote:
> > >
> > > Hi Marc,
> > >
> > > We have an SoC that use GIC-700, but not support shareability,
> > 
> > Define this. The IP does support shareability, but your integration doesn't?
> > 
> > > Currently I just hack the code as below. Do you think it is feasible
> > > to add firmware bindings such that these can be used to define the
> > > correct shareability/cacheability instead of relying on the
> > > programmability of the CBASER register?
> > >
> > > Saying with "broken-shareability", we just clear all the shareability
> > > settings.
> > 
> > This is the same thing as the Rockchip crap, so you are in good company.
> > 
> > I've repeatedly stated that this needs to be handled:
> > 
> > - either by describing the full system topology and describe what is
> >   in the same inner-shareable domain as the CPUs, which needs to
> >   encompass both DT and ACPI (starting with DT seems reasonable),
> > 
> 
> We will give a look on this. But honestly not have a good idea on how.

For each node that can initiate memory transactions in the system, you
have a phandle to a node that describe the shareability. In your case,
you would have two nodes: one inner-shareable with at least the CPUs
and whatever IP block that is in the same IS domain, and another that
describe the outer-shareable domain.

Or another variation on the same theme.

	M.

-- 
Without deviation from the norm, progress is not possible.