linux-kernel - RE: gic700 shareability question

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Message-ID: <DU0PR04MB9417FCF524FA0BB9808B4E8088929@DU0PR04MB9417.eurprd04.prod.outlook.com>
Date:   Mon, 3 Apr 2023 01:36:31 +0000
From:   Peng Fan <peng.fan@....com>
To:     Marc Zyngier <maz@...nel.org>,
        Lorenzo Pieralisi <lpieralisi@...nel.org>
CC:     "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: gic700 shareability question

Hi Marc,

> Subject: Re: gic700 shareability question
> 
> + Lorenzo
> 
> On Tue, 28 Mar 2023 13:48:19 +0100,
> Peng Fan <peng.fan@....com> wrote:
> >
> > Hi Marc,
> >
> > We have an SoC that use GIC-700, but not support shareability,
> 
> Define this. The IP does support shareability, but your integration doesn't?
> 
> > Currently I just hack the code as below. Do you think it is feasible
> > to add firmware bindings such that these can be used to define the
> > correct shareability/cacheability instead of relying on the
> > programmability of the CBASER register?
> >
> > Saying with "broken-shareability", we just clear all the shareability
> > settings.
> 
> This is the same thing as the Rockchip crap, so you are in good company.
> 
> I've repeatedly stated that this needs to be handled:
> 
> - either by describing the full system topology and describe what is
>   in the same inner-shareable domain as the CPUs, which needs to
>   encompass both DT and ACPI (starting with DT seems reasonable),
> 

We will give a look on this. But honestly not have a good idea on how.

> - or as a SoC specific erratum, but not as a general "sh*t happened"
>   property.

I will ask the hardware team to create an errata.
> 
> AFAIK, Lorenzo is looking into this.

Lorenzo, are you working on this? 

Thanks,
Peng.
> 
> 	M.
> 
> --
> Without deviation from the norm, progress is not possible.