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Message-ID: <a23f486a-e08f-f1ce-5f1b-bc34e4c92e67@pengutronix.de>
Date: Mon, 3 Apr 2023 10:34:09 +0200
From: Ahmad Fatoum <a.fatoum@...gutronix.de>
To: "Peng Fan (OSS)" <peng.fan@....nxp.com>, abelvesa@...nel.org,
mturquette@...libre.com, sboyd@...nel.org, shawnguo@...nel.org,
s.hauer@...gutronix.de, kernel@...gutronix.de, festevam@...il.com
Cc: Peng Fan <peng.fan@....com>, Shengjiu Wang <shengjiu.wang@....com>,
linux-kernel@...r.kernel.org, linux-imx@....com,
linux-clk@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH V2] clk: imx: imx6sx: spdif clock rate is too high for
asrc
Hello Peng,
On 03.04.23 10:21, Peng Fan (OSS) wrote:
> From: Shengjiu Wang <shengjiu.wang@....com>
>
> spdif clock is one of the asrc clock source, which is used
> for ideal ratio mode. when set to 98.304MHz, it cause the
> divider of asrc input clock and output clock exceed the
> maximum value, and asrc driver saturate the value to maximum
> value, which will cause the ASRC's performance very bad.
> So we need to set spdif clock to a proper rate. which make asrc
> divider not exceed maximum value, at least one of divider not
> exceed maximum value.
> The target is spdif clock rate / output(or input) sample rate
> less than 1024(which is maximum divider).
>
> Fixes: f1541e15e38e ("clk: imx6sx: Switch to clk_hw based API")
Before referenced commit, it looked like this:
clk_set_rate(clks[IMX6SX_CLK_SPDIF_PODF], 98304000);
I think commit d55135689019 ("ARM: imx: add clock driver for imx6sx")
is what you're after.
Cheers,
Ahmad
> Signed-off-by: Shengjiu Wang <shengjiu.wang@....com>
> Signed-off-by: Peng Fan <peng.fan@....com>
> ---
>
> V2:
> Add Fixes tag
>
> drivers/clk/imx/clk-imx6sx.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/imx/clk-imx6sx.c b/drivers/clk/imx/clk-imx6sx.c
> index 7cf86707bc39..3face052527d 100644
> --- a/drivers/clk/imx/clk-imx6sx.c
> +++ b/drivers/clk/imx/clk-imx6sx.c
> @@ -520,7 +520,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
> clk_set_rate(hws[IMX6SX_CLK_PLL4_AUDIO_DIV]->clk, 393216000);
>
> clk_set_parent(hws[IMX6SX_CLK_SPDIF_SEL]->clk, hws[IMX6SX_CLK_PLL4_AUDIO_DIV]->clk);
> - clk_set_rate(hws[IMX6SX_CLK_SPDIF_PODF]->clk, 98304000);
> + clk_set_rate(hws[IMX6SX_CLK_SPDIF_PODF]->clk, 24576000);
>
> clk_set_parent(hws[IMX6SX_CLK_AUDIO_SEL]->clk, hws[IMX6SX_CLK_PLL3_USB_OTG]->clk);
> clk_set_rate(hws[IMX6SX_CLK_AUDIO_PODF]->clk, 24000000);
--
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