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Message-ID: <20230405125759.4201-3-quic_kriskura@quicinc.com>
Date: Wed, 5 Apr 2023 18:27:53 +0530
From: Krishna Kurapati <quic_kriskura@...cinc.com>
To: Thinh Nguyen <Thinh.Nguyen@...opsys.com>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Philipp Zabel <p.zabel@...gutronix.de>,
"Andy Gross" <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
"Konrad Dybcio" <konrad.dybcio@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>
CC: <linux-usb@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
<quic_pkondeti@...cinc.com>, <quic_ppratap@...cinc.com>,
<quic_wcheng@...cinc.com>, <quic_jackp@...cinc.com>,
<quic_harshq@...cinc.com>, <ahalaney@...hat.com>,
<quic_shazhuss@...cinc.com>,
Krishna Kurapati <quic_kriskura@...cinc.com>
Subject: [PATCH v6 2/8] usb: dwc3: core: Access XHCI address space temporarily to read port info
Currently host-only capable DWC3 controllers support Multiport. Temporarily
map XHCI address space for host-only controllers and parse XHCI Extended
Capabilities registers to read number of usb2 ports and usb3 ports present on
multiport controller. Each USB Port is atleast HS capable.
The port info for usb2 and usb3 phy are identified as num_usb2_ports and
num_usb3_ports. The intention is as follows:
Wherever we need to perform phy operations like:
LOOP_OVER_NUMBER_OF_AVAILABLE_PORTS()
{
phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
}
If number of usb2 ports is 3, loop can go from index 0-2 for usb2_generic_phy.
If number of usb3-ports is 2, we don't know for sure, if the first 2 ports are
SS capable or some other ports like (2 and 3) are SS capable. So instead,
num_usb2_ports is used to loop around all phy's (both hs and ss) for
performing phy operations. If any usb3_generic_phy turns out to be NULL, phy
operation just bails out.
num_usb3_ports is used to modify GUSB3PIPECTL registers while setting up
phy's as we need to know how many SS capable ports are there for this.
Signed-off-by: Krishna Kurapati <quic_kriskura@...cinc.com>
---
Link to v5: https://lore.kernel.org/all/20230310163420.7582-3-quic_kriskura@quicinc.com/
drivers/usb/dwc3/core.c | 69 +++++++++++++++++++++++++++++++++++++++++
drivers/usb/dwc3/core.h | 60 +++++++++++++++++++++++++++++++++++
2 files changed, 129 insertions(+)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 476b63618511..567ae79389a1 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -1750,6 +1750,60 @@ static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc)
return edev;
}
+static int dwc3_read_port_info(struct dwc3 *dwc)
+{
+ void __iomem *regs;
+ u32 offset;
+ u32 temp;
+ u8 major_revision;
+ int ret = 0;
+
+ /*
+ * Remap xHCI address space to access XHCI ext cap regs,
+ * since it is needed to get port info.
+ */
+ regs = ioremap(dwc->xhci_resources[0].start,
+ resource_size(&dwc->xhci_resources[0]));
+ if (IS_ERR(regs)) {
+ return PTR_ERR(regs);
+ }
+
+ offset = dwc3_xhci_find_next_ext_cap(regs, 0,
+ XHCI_EXT_CAPS_PROTOCOL);
+ while (offset) {
+ temp = readl(regs + offset);
+ major_revision = XHCI_EXT_PORT_MAJOR(temp);;
+
+ temp = readl(regs + offset + 0x08);
+ if (major_revision == 0x03) {
+ dwc->num_usb3_ports += XHCI_EXT_PORT_COUNT(temp);
+ } else if (major_revision <= 0x02) {
+ dwc->num_usb2_ports += XHCI_EXT_PORT_COUNT(temp);
+ } else {
+ dev_err(dwc->dev, "port revision seems wrong\n");
+ ret = -EINVAL;
+ goto unmap_reg;
+ }
+
+ offset = dwc3_xhci_find_next_ext_cap(regs, offset,
+ XHCI_EXT_CAPS_PROTOCOL);
+ }
+
+ temp = readl(regs + DWC3_XHCI_HCSPARAMS1);
+ if (HCS_MAX_PORTS(temp) != (dwc->num_usb3_ports + dwc->num_usb2_ports)) {
+ dev_err(dwc->dev, "inconsistency in port info\n");
+ ret = -EINVAL;
+ goto unmap_reg;
+ }
+
+ dev_dbg(dwc->dev,
+ "hs-ports: %d ss-ports: %d\n", dwc->num_usb2_ports, dwc->num_usb3_ports);
+
+unmap_reg:
+ iounmap(regs);
+ return ret;
+}
+
static int dwc3_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -1757,6 +1811,7 @@ static int dwc3_probe(struct platform_device *pdev)
struct dwc3 *dwc;
int ret;
+ unsigned int hw_mode;
void __iomem *regs;
@@ -1880,6 +1935,20 @@ static int dwc3_probe(struct platform_device *pdev)
goto disable_clks;
}
+ /*
+ * Currently DWC3 controllers that are host-only capable
+ * support Multiport
+ */
+ hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
+ if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) {
+ ret = dwc3_read_port_info(dwc);
+ if (ret)
+ goto disable_clks;
+ } else {
+ dwc->num_usb2_ports = 1;
+ dwc->num_usb3_ports = 1;
+ }
+
spin_lock_init(&dwc->lock);
mutex_init(&dwc->mutex);
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 4743e918dcaf..229b7da8c5bc 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -35,6 +35,17 @@
#define DWC3_MSG_MAX 500
+/* Define XHCI Extcap register offsets for getting multiport info */
+#define XHCI_HCC_PARAMS_OFFSET 0x10
+#define DWC3_XHCI_HCSPARAMS1 0x04
+#define XHCI_EXT_CAPS_PROTOCOL 2
+#define XHCI_HCC_EXT_CAPS(p) (((p)>>16)&0xffff)
+#define XHCI_EXT_CAPS_ID(p) (((p)>>0)&0xff)
+#define XHCI_EXT_CAPS_NEXT(p) (((p)>>8)&0xff)
+#define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
+#define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
+#define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
+
/* Global constants */
#define DWC3_PULL_UP_TIMEOUT 500 /* ms */
#define DWC3_BOUNCE_SIZE 1024 /* size of a superspeed bulk */
@@ -1023,6 +1034,10 @@ struct dwc3_scratchpad_array {
* @usb_psy: pointer to power supply interface.
* @usb2_phy: pointer to USB2 PHY
* @usb3_phy: pointer to USB3 PHY
+ * @num_usb2_ports: Indicates the number of usb2 ports to be serviced by the
+ * controller.
+ * @num_usb3_ports: Indicates the number of usb3 ports to be serviced by the
+ * controller.
* @usb2_generic_phy: pointer to USB2 PHY
* @usb3_generic_phy: pointer to USB3 PHY
* @phys_ready: flag to indicate that PHYs are ready
@@ -1158,6 +1173,8 @@ struct dwc3 {
struct usb_phy *usb2_phy;
struct usb_phy *usb3_phy;
+ u32 num_usb2_ports;
+ u32 num_usb3_ports;
struct phy *usb2_generic_phy;
struct phy *usb3_generic_phy;
@@ -1645,4 +1662,47 @@ static inline void dwc3_ulpi_exit(struct dwc3 *dwc)
{ }
#endif
+/**
+ * Find the offset of the extended capabilities with capability ID id.
+ *
+ * @base PCI MMIO registers base address.
+ * @start address at which to start looking, (0 or HCC_PARAMS to start at
+ * beginning of list)
+ * @id Extended capability ID to search for, or 0 for the next
+ * capability
+ *
+ * Returns the offset of the next matching extended capability structure.
+ * Some capabilities can occur several times, e.g., the XHCI_EXT_CAPS_PROTOCOL,
+ * and this provides a way to find them all.
+ */
+
+static inline int dwc3_xhci_find_next_ext_cap(void __iomem *base, u32 start, int id)
+{
+ u32 val;
+ u32 next;
+ u32 offset;
+
+ offset = start;
+ if (!start || start == XHCI_HCC_PARAMS_OFFSET) {
+ val = readl(base + XHCI_HCC_PARAMS_OFFSET);
+ if (val == ~0)
+ return 0;
+ offset = XHCI_HCC_EXT_CAPS(val) << 2;
+ if (!offset)
+ return 0;
+ }
+ do {
+ val = readl(base + offset);
+ if (val == ~0)
+ return 0;
+ if (offset != start && (id == 0 || XHCI_EXT_CAPS_ID(val) == id))
+ return offset;
+
+ next = XHCI_EXT_CAPS_NEXT(val);
+ offset += next << 2;
+ } while (next);
+
+ return 0;
+}
+
#endif /* __DRIVERS_USB_DWC3_CORE_H */
--
2.40.0
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