[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <ae04df79-10d6-6a38-715b-8f00e8764d85@linaro.org>
Date: Thu, 6 Apr 2023 22:38:51 +0200
From: Konrad Dybcio <konrad.dybcio@...aro.org>
To: Devi Priya <quic_devipriy@...cinc.com>, agross@...nel.org,
andersson@...nel.org, mturquette@...libre.com, sboyd@...nel.org,
robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
jassisinghbrar@...il.com, catalin.marinas@....com, will@...nel.org,
dmitry.baryshkov@...aro.org, arnd@...db.de,
geert+renesas@...der.be, nfraprado@...labora.com,
broonie@...nel.org, rafal@...ecki.pl,
linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org
Cc: quic_srichara@...cinc.com, quic_sjaganat@...cinc.com,
quic_kathirav@...cinc.com, quic_arajkuma@...cinc.com,
quic_anusha@...cinc.com, quic_ipkumar@...cinc.com
Subject: Re: [PATCH V3 2/5] clk: qcom: apss-ipq-pll: Add support for IPQ9574
On 6.04.2023 08:13, Devi Priya wrote:
> Add the compatible and configuration values for A73 Huayra PLL found
> on IPQ9574.
>
> Co-developed-by: Praveenkumar I <quic_ipkumar@...cinc.com>
> Signed-off-by: Praveenkumar I <quic_ipkumar@...cinc.com>
> Signed-off-by: Devi Priya <quic_devipriy@...cinc.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@...aro.org>
Konrad
> Changes in V3:
> - Updated the subject and aligned the commit message
>
> drivers/clk/qcom/apss-ipq-pll.c | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/drivers/clk/qcom/apss-ipq-pll.c b/drivers/clk/qcom/apss-ipq-pll.c
> index cf4f0d340cbf..ce28d882ee78 100644
> --- a/drivers/clk/qcom/apss-ipq-pll.c
> +++ b/drivers/clk/qcom/apss-ipq-pll.c
> @@ -111,6 +111,18 @@ static const struct alpha_pll_config ipq8074_pll_config = {
> .test_ctl_hi_val = 0x4000,
> };
>
> +static const struct alpha_pll_config ipq9574_pll_config = {
> + .l = 0x3b,
> + .config_ctl_val = 0x200d4828,
> + .config_ctl_hi_val = 0x6,
> + .early_output_mask = BIT(3),
> + .aux2_output_mask = BIT(2),
> + .aux_output_mask = BIT(1),
> + .main_output_mask = BIT(0),
> + .test_ctl_val = 0x0,
> + .test_ctl_hi_val = 0x4000,
> +};
> +
> struct apss_pll_data {
> int pll_type;
> struct clk_alpha_pll *pll;
> @@ -135,6 +147,12 @@ static struct apss_pll_data ipq6018_pll_data = {
> .pll_config = &ipq6018_pll_config,
> };
>
> +static struct apss_pll_data ipq9574_pll_data = {
> + .pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA,
> + .pll = &ipq_pll_huayra,
> + .pll_config = &ipq9574_pll_config,
> +};
> +
> static const struct regmap_config ipq_pll_regmap_config = {
> .reg_bits = 32,
> .reg_stride = 4,
> @@ -180,6 +198,7 @@ static const struct of_device_id apss_ipq_pll_match_table[] = {
> { .compatible = "qcom,ipq5332-a53pll", .data = &ipq5332_pll_data },
> { .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_data },
> { .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_data },
> + { .compatible = "qcom,ipq9574-a73pll", .data = &ipq9574_pll_data },
> { }
> };
> MODULE_DEVICE_TABLE(of, apss_ipq_pll_match_table);
Powered by blists - more mailing lists