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Message-ID: <trinity-3aa9784a-714a-47cd-866b-3ae77ecca0fb-1680773596235@3c-app-gmx-bap56>
Date: Thu, 6 Apr 2023 11:33:16 +0200
From: hfdevel@....net
To: neil.armstrong@...aro.org, khilman@...libre.com,
jbrunet@...libre.com, martin.blumenstingl@...glemail.com
Cc: linux-kernel@...r.kernel.org
Subject: [PATCH] correct uart_B and uart_C clock references for meson8b
commit b3b6a88d2347d2ec9075603920e616836cb46750
Author: Hans-Frieder Vogt <hfdevel@....net>
Date: Thu Apr 6 10:21:49 2023 +0200
[PATCH] correct uart_B and uart_C clock references for meson8b
with the current device tree for meson8b, uarts B (e.g. available on pins 8/10 on Odroid-C1) and C (pins 3/5 on Odroid-C1) do not work, because they are relying on incorrect clocks.
This trivial patch changes the references of pclk to the correct CLKID, which allows to use the two uarts.
Signed-off-by: Hans-Frieder Vogt <hfdevel@....net>
---
meson8b.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index d5a3fe21e8e7..25f7c985f9ea 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -740,13 +740,13 @@ &uart_A {
&uart_B {
compatible = "amlogic,meson8b-uart";
- clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>;
+ clocks = <&xtal>, <&clkc CLKID_UART1>, <&clkc CLKID_CLK81>;
clock-names = "xtal", "pclk", "baud";
};
&uart_C {
compatible = "amlogic,meson8b-uart";
- clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>;
+ clocks = <&xtal>, <&clkc CLKID_UART2>, <&clkc CLKID_CLK81>;
clock-names = "xtal", "pclk", "baud";
};
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