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Date:   Thu, 6 Apr 2023 15:58:00 +0200
From:   Konrad Dybcio <konrad.dybcio@...aro.org>
To:     Bhupesh Sharma <bhupesh.sharma@...aro.org>,
        linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org
Cc:     agross@...nel.org, linux-kernel@...r.kernel.org,
        linux-crypto@...r.kernel.org, andersson@...nel.org,
        bhupesh.linux@...il.com, krzysztof.kozlowski@...aro.org,
        robh+dt@...nel.org, vladimir.zapolskiy@...aro.org,
        rfoss@...nel.org, neil.armstrong@...aro.org, djakov@...nel.org
Subject: Re: [PATCH v6 08/11] arm64: dts: qcom: sm8150: Add Crypto Engine
 support



On 5.04.2023 09:28, Bhupesh Sharma wrote:
> Add crypto engine (CE) and CE BAM related nodes and definitions to
> 'sm8150.dtsi'.
> 
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@...aro.org>
> ---
>  arch/arm64/boot/dts/qcom/sm8150.dtsi | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> index 9491be4a6bf0..c104d0b12dc6 100644
> --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> @@ -2081,6 +2081,28 @@ ufs_mem_phy_lanes: phy@...7400 {
>  			};
>  		};
>  
> +		cryptobam: dma-controller@...4000 {
> +			compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
> +			reg = <0 0x01dc4000 0 0x24000>;
> +			interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
> +			#dma-cells = <1>;
> +			qcom,ee = <0>;
> +			qcom,controlled-remotely;
> +			iommus = <&apps_smmu 0x514 0x0011>,
> +				 <&apps_smmu 0x516 0x0011>;
> +		};
> +
> +		crypto: crypto@...a000 {
> +			compatible = "qcom,sm8150-qce", "qcom,qce";
> +			reg = <0 0x01dfa000 0 0x6000>;
> +			dmas = <&cryptobam 4>, <&cryptobam 5>;
> +			dma-names = "rx", "tx";
> +			iommus = <&apps_smmu 0x514 0x0011>,
> +				 <&apps_smmu 0x516 0x0011>;
Downstream uses these (sid, mask) combos:

qcedev:
0x0506 0x0011 
0x0516 0x0011 // equal to 0x506 0x11

qcom_cedev_ns_cb:
0x512 0
0x518 0
0x519 0
0x51f 0

Shouldn't we use them too?

Konrad

> +			interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>;
> +			interconnect-names = "memory";
> +		};
> +
>  		tcsr_mutex: hwlock@...0000 {
>  			compatible = "qcom,tcsr-mutex";
>  			reg = <0x0 0x01f40000 0x0 0x20000>;

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