linux-kernel - Re: [PATCH v6 09/11] arm64: dts: qcom: sm8250: Add Crypto Engine support

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <af22628c-e54b-f7e1-16a6-6534f4526cd5@linaro.org>
Date:   Thu, 6 Apr 2023 15:59:40 +0200
From:   Konrad Dybcio <konrad.dybcio@...aro.org>
To:     Bhupesh Sharma <bhupesh.sharma@...aro.org>,
        linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org
Cc:     agross@...nel.org, linux-kernel@...r.kernel.org,
        linux-crypto@...r.kernel.org, andersson@...nel.org,
        bhupesh.linux@...il.com, krzysztof.kozlowski@...aro.org,
        robh+dt@...nel.org, vladimir.zapolskiy@...aro.org,
        rfoss@...nel.org, neil.armstrong@...aro.org, djakov@...nel.org
Subject: Re: [PATCH v6 09/11] arm64: dts: qcom: sm8250: Add Crypto Engine
 support



On 5.04.2023 09:28, Bhupesh Sharma wrote:
> Add crypto engine (CE) and CE BAM related nodes and definitions to
> 'sm8250.dtsi'.
> 
> Co-developed-by and Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@...aro.org>
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@...aro.org>
> ---
>  arch/arm64/boot/dts/qcom/sm8250.dtsi | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> index 7b78761f2041..2f6b8d4a2d41 100644
> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> @@ -2222,6 +2222,28 @@ ufs_mem_phy_lanes: phy@...7400 {
>  			};
>  		};
>  
> +		cryptobam: dma-controller@...4000 {
> +			compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
> +			reg = <0 0x01dc4000 0 0x24000>;
> +			interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
> +			#dma-cells = <1>;
> +			qcom,ee = <0>;
> +			qcom,controlled-remotely;
> +			iommus = <&apps_smmu 0x594 0x0011>,
> +				 <&apps_smmu 0x596 0x0011>;
> +		};
> +
> +		crypto: crypto@...a000 {
> +			compatible = "qcom,sm8250-qce", "qcom,sm8150-qce", "qcom,qce";
> +			reg = <0 0x01dfa000 0 0x6000>;
> +			dmas = <&cryptobam 4>, <&cryptobam 5>;
> +			dma-names = "rx", "tx";
> +			iommus = <&apps_smmu 0x594 0x0011>,
> +				 <&apps_smmu 0x596 0x0011>;
> +			interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>;
> +			interconnect-names = "memory";
Shouldn't we also attach the contexts from qcom_cedev_ns_cb{}?

Konrad
> +		};
> +
>  		tcsr_mutex: hwlock@...0000 {
>  			compatible = "qcom,tcsr-mutex";
>  			reg = <0x0 0x01f40000 0x0 0x40000>;