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Message-ID: <ZDbZA3AnbTTylFdb@matsya>
Date: Wed, 12 Apr 2023 21:44:59 +0530
From: Vinod Koul <vkoul@...nel.org>
To: Bartosz Golaszewski <brgl@...ev.pl>
Cc: Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Kishon Vijay Abraham I <kishon@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Manivannan Sadhasivam <mani@...nel.org>,
Alim Akhtar <alim.akhtar@...sung.com>,
Avri Altman <avri.altman@....com>,
Bart Van Assche <bvanassche@....org>,
linux-arm-msm@...r.kernel.org, linux-phy@...ts.infradead.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-scsi@...r.kernel.org,
Bartosz Golaszewski <bartosz.golaszewski@...aro.org>
Subject: Re: [PATCH v3 3/5] phy: qualcomm: phy-qcom-qmp-ufs: add definitions
for sa8775p
On 11-04-23, 15:04, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <bartosz.golaszewski@...aro.org>
>
> Add QMP PHY config for sa8775p and add support for the new compatible.
>
> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@...aro.org>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 38 +++++++++++++++++++++++++
> 1 file changed, 38 insertions(+)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> index d58822049211..5612282eb378 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> @@ -853,6 +853,41 @@ static const struct qmp_phy_cfg msm8996_ufsphy_cfg = {
> .no_pcs_sw_reset = true,
> };
>
> +
There was already an empty line, this didnt make sense. Please run
checkpatch to avoid missing these style issues
I have fixed it up and applied
> +static const struct qmp_phy_cfg sa8775p_ufsphy_cfg = {
> + .lanes = 2,
> +
> + .offsets = &qmp_ufs_offsets,
> +
> + .tbls = {
> + .serdes = sm8350_ufsphy_serdes,
> + .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
> + .tx = sm8350_ufsphy_tx,
> + .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx),
> + .rx = sm8350_ufsphy_rx,
> + .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx),
> + .pcs = sm8350_ufsphy_pcs,
> + .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
> + },
> + .tbls_hs_b = {
> + .serdes = sm8350_ufsphy_hs_b_serdes,
> + .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
> + },
> + .tbls_hs_g4 = {
> + .tx = sm8350_ufsphy_g4_tx,
> + .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
> + .rx = sm8350_ufsphy_g4_rx,
> + .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
> + .pcs = sm8350_ufsphy_g4_pcs,
> + .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
> + },
> + .clk_list = sm8450_ufs_phy_clk_l,
> + .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = ufsphy_v5_regs_layout,
> +};
> +
> static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
> .lanes = 2,
>
> @@ -1600,6 +1635,9 @@ static const struct of_device_id qmp_ufs_of_match_table[] = {
> }, {
> .compatible = "qcom,msm8998-qmp-ufs-phy",
> .data = &sdm845_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sa8775p-qmp-ufs-phy",
> + .data = &sa8775p_ufsphy_cfg,
> }, {
> .compatible = "qcom,sc8180x-qmp-ufs-phy",
> .data = &sm8150_ufsphy_cfg,
> --
> 2.37.2
--
~Vinod
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