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Date:   Fri, 14 Apr 2023 13:31:42 +0200
From:   Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To:     Bharat Bhushan <bbhushan2@...vell.com>,
        "wim@...ux-watchdog.org" <wim@...ux-watchdog.org>,
        "linux@...ck-us.net" <linux@...ck-us.net>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "krzysztof.kozlowski+dt@...aro.org" 
        <krzysztof.kozlowski+dt@...aro.org>,
        "linux-watchdog@...r.kernel.org" <linux-watchdog@...r.kernel.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [EXT] Re: [PATCH 1/2] dt-bindings: watchdog: marvell octeonTX2
 GTI system atchdog driver

On 14/04/2023 13:29, Bharat Bhushan wrote:

> 
>>
>>> +
>>> +examples:
>>> +  - |
>>> +    soc {
>>> +        #address-cells = <2>;
>>> +        #size-cells = <2>;
>>> +
>>> +        watchdog@...000040000 {
>>> +          compatible = "marvell-octeontx2-wdt";
>>> +          reg = <0x8020 0x40000 0x0 0x20000>;
>>
>> Are you sure that this is correct DTS? 32-bit numbers are usually 8-digit long. Plus
>> size of 0x20000 is crazy huge. And the unit address is a bit unusual. Are you sure
>> dtc W=1 does not say about any errors in your DTS?
> 
> Each cell is 32bit, so if we specify less than upper values becomes zeros (0s). 

... and what is the convention/coding style of your subarch? Is to have
short or 0-padded reg addresses?

Anyway, I have doubts this was tested, so please confirm that dtbs W=1
and dtbs_check produce no errors on your DTS. BTW, where is the DTS?

Best regards,
Krzysztof

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