linux-kernel - Re: [PATCH] x86/mce: Schedule mce_setup() on correct CPU for CPER decoding

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Message-ID: <7b316c31-ded2-d6d5-0315-dd4906ff833b@amd.com>
Date:   Mon, 17 Apr 2023 13:28:44 -0400
From:   Yazen Ghannam <yazen.ghannam@....com>
To:     "Luck, Tony" <tony.luck@...el.com>,
        "linux-edac@...r.kernel.org" <linux-edac@...r.kernel.org>
Cc:     yazen.ghannam@....com,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "x86@...nel.org" <x86@...nel.org>
Subject: Re: [PATCH] x86/mce: Schedule mce_setup() on correct CPU for CPER
 decoding

On 4/17/23 13:17, Luck, Tony wrote:
>> int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info, u64 lapic_id)
> 
> I'm a bit puzzled why this function has "smca" in the name. I think it is called
> unconditionally on Intel as well as AMD systems ... and looks like it will do useful
> things if Intel someday has a hybrid server that reports APEI errors (maybe it is
> already useful on hybrid clients?).
> 
> Otherwise this look looks fine.
> 
> Acked-by: Tony Luck <tony.luck@...el.com>
> 

Thanks Tony.

The function expects the data to match the "MCAX" register layout used on
Scalable MCA systems. CTL, STATUS, ADDR, and MISC will be at the same offsets
for legacy MCA and MCAX. But the rest will be different.

This could be extended though, if other systems will use it.

Thanks,
Yazen