linux-kernel - RE: [PATCH] x86/mce: Schedule mce_setup() on correct CPU for CPER decoding

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Message-ID: <SJ1PR11MB60837EAC6B0AA28AF7D16784FC9C9@SJ1PR11MB6083.namprd11.prod.outlook.com>
Date:   Mon, 17 Apr 2023 17:39:50 +0000
From:   "Luck, Tony" <tony.luck@...el.com>
To:     Yazen Ghannam <yazen.ghannam@....com>,
        "linux-edac@...r.kernel.org" <linux-edac@...r.kernel.org>
CC:     "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "x86@...nel.org" <x86@...nel.org>
Subject: RE: [PATCH] x86/mce: Schedule mce_setup() on correct CPU for CPER
 decoding

> The function expects the data to match the "MCAX" register layout used on
> Scalable MCA systems. CTL, STATUS, ADDR, and MISC will be at the same offsets
> for legacy MCA and MCAX. But the rest will be different.

Ah yes. Looking at the code, rather than the patch I see that it first checks for SMCA
and returns if it isn't on an SMCA system.

        if (!boot_cpu_has(X86_FEATURE_SMCA))
                return -EINVAL;

> This could be extended though, if other systems will use it.

I'll keep it in mind if Intel makes a hybrid server.

-Tony