linux-kernel - Re: [PATCH] x86/mce: Schedule mce_setup() on correct CPU for CPER decoding

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Message-ID: <96f6201e-8c33-a25d-7ec3-00769f67869a@amd.com>
Date:   Fri, 9 Jun 2023 10:26:54 -0400
From:   Yazen Ghannam <yazen.ghannam@....com>
To:     "Luck, Tony" <tony.luck@...el.com>,
        "linux-edac@...r.kernel.org" <linux-edac@...r.kernel.org>
Cc:     yazen.ghannam@....com,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "x86@...nel.org" <x86@...nel.org>
Subject: Re: [PATCH] x86/mce: Schedule mce_setup() on correct CPU for CPER
 decoding

On 4/17/23 1:39 PM, Luck, Tony wrote:
>> The function expects the data to match the "MCAX" register layout used on
>> Scalable MCA systems. CTL, STATUS, ADDR, and MISC will be at the same offsets
>> for legacy MCA and MCAX. But the rest will be different.
> 
> Ah yes. Looking at the code, rather than the patch I see that it first checks for SMCA
> and returns if it isn't on an SMCA system.
> 
>         if (!boot_cpu_has(X86_FEATURE_SMCA))
>                 return -EINVAL;
> 
>> This could be extended though, if other systems will use it.
> 
> I'll keep it in mind if Intel makes a hybrid server.
>

Hi all,

Any further comments on this?

Thanks,
Yazen