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Message-ID: <CAPDyKFqRy=gCPiRfPs6DrgmjGFPazi-HQeG0fSjqSe3vFE9pjA@mail.gmail.com>
Date: Mon, 17 Apr 2023 16:54:10 +0200
From: Ulf Hansson <ulf.hansson@...aro.org>
To: Brad Larson <blarson@....com>
Cc: linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-mmc@...r.kernel.org, linux-spi@...r.kernel.org,
adrian.hunter@...el.com, alcooperx@...il.com,
andy.shevchenko@...il.com, arnd@...db.de,
brendan.higgins@...ux.dev, briannorris@...omium.org,
brijeshkumar.singh@....com, catalin.marinas@....com,
davidgow@...gle.com, gsomlo@...il.com, gerg@...ux-m68k.org,
krzk@...nel.org, krzysztof.kozlowski+dt@...aro.org, lee@...nel.org,
lee.jones@...aro.org, broonie@...nel.org,
yamada.masahiro@...ionext.com, p.zabel@...gutronix.de,
piotrs@...ence.com, p.yadav@...com, rdunlap@...radead.org,
robh+dt@...nel.org, samuel@...lland.org, fancer.lancer@...il.com,
skhan@...uxfoundation.org, suravee.suthikulpanit@....com,
thomas.lendacky@....com, tonyhuang.sunplus@...il.com,
vaishnav.a@...com, will@...nel.org, devicetree@...r.kernel.org
Subject: Re: [PATCH v13 11/15] mmc: sdhci-cadence: Enable device specific
override of writel()
On Mon, 10 Apr 2023 at 20:47, Brad Larson <blarson@....com> wrote:
>
> SoCs with device specific Cadence implementation, such as setting
> byte-enables before the write, need to override writel(). Add a
> callback where the default is writel() for all existing chips.
>
> Signed-off-by: Brad Larson <blarson@....com>
> Acked-by: Adrian Hunter <adrian.hunter@...el.com>
Applied for next, thanks!
Kind regards
Uffe
> ---
>
> v10 changes:
> - The 1st patch adding private writel() is unchanged. The 2nd patch is split
> into two patches to provide for device specific init in one patch with no
> effect on existing designs. Then add the pensando support into the next patch.
> Then the 4th patch is mmc hardware reset support which is unchanged.
>
> v9 changes:
> - No change to this patch but as some patches are deleted and this is
> a respin the three successive patches to sdhci-cadence.c are
> patches 12, 13, and 14 which do the following:
>
> 1. Add ability for Cadence specific design to have priv writel().
> 2. Add Elba SoC support that requires its own priv writel() for
> byte-lane control .
> 3. Add support for mmc hardware reset.
>
> ---
> drivers/mmc/host/sdhci-cadence.c | 18 +++++++++++++-----
> 1 file changed, 13 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c
> index 6f2de54a5987..708d4297f241 100644
> --- a/drivers/mmc/host/sdhci-cadence.c
> +++ b/drivers/mmc/host/sdhci-cadence.c
> @@ -67,6 +67,7 @@ struct sdhci_cdns_phy_param {
> struct sdhci_cdns_priv {
> void __iomem *hrs_addr;
> bool enhanced_strobe;
> + void (*priv_writel)(struct sdhci_cdns_priv *priv, u32 val, void __iomem *reg);
> unsigned int nr_phy_params;
> struct sdhci_cdns_phy_param phy_params[];
> };
> @@ -90,6 +91,12 @@ static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = {
> { "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, },
> };
>
> +static inline void cdns_writel(struct sdhci_cdns_priv *priv, u32 val,
> + void __iomem *reg)
> +{
> + writel(val, reg);
> +}
> +
> static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv,
> u8 addr, u8 data)
> {
> @@ -104,17 +111,17 @@ static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv,
>
> tmp = FIELD_PREP(SDHCI_CDNS_HRS04_WDATA, data) |
> FIELD_PREP(SDHCI_CDNS_HRS04_ADDR, addr);
> - writel(tmp, reg);
> + priv->priv_writel(priv, tmp, reg);
>
> tmp |= SDHCI_CDNS_HRS04_WR;
> - writel(tmp, reg);
> + priv->priv_writel(priv, tmp, reg);
>
> ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 0, 10);
> if (ret)
> return ret;
>
> tmp &= ~SDHCI_CDNS_HRS04_WR;
> - writel(tmp, reg);
> + priv->priv_writel(priv, tmp, reg);
>
> ret = readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS04_ACK),
> 0, 10);
> @@ -191,7 +198,7 @@ static void sdhci_cdns_set_emmc_mode(struct sdhci_cdns_priv *priv, u32 mode)
> tmp = readl(priv->hrs_addr + SDHCI_CDNS_HRS06);
> tmp &= ~SDHCI_CDNS_HRS06_MODE;
> tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_MODE, mode);
> - writel(tmp, priv->hrs_addr + SDHCI_CDNS_HRS06);
> + priv->priv_writel(priv, tmp, priv->hrs_addr + SDHCI_CDNS_HRS06);
> }
>
> static u32 sdhci_cdns_get_emmc_mode(struct sdhci_cdns_priv *priv)
> @@ -223,7 +230,7 @@ static int sdhci_cdns_set_tune_val(struct sdhci_host *host, unsigned int val)
> */
> for (i = 0; i < 2; i++) {
> tmp |= SDHCI_CDNS_HRS06_TUNE_UP;
> - writel(tmp, reg);
> + priv->priv_writel(priv, tmp, reg);
>
> ret = readl_poll_timeout(reg, tmp,
> !(tmp & SDHCI_CDNS_HRS06_TUNE_UP),
> @@ -386,6 +393,7 @@ static int sdhci_cdns_probe(struct platform_device *pdev)
> priv->nr_phy_params = nr_phy_params;
> priv->hrs_addr = host->ioaddr;
> priv->enhanced_strobe = false;
> + priv->priv_writel = cdns_writel;
> host->ioaddr += SDHCI_CDNS_SRS_BASE;
> host->mmc_host_ops.hs400_enhanced_strobe =
> sdhci_cdns_hs400_enhanced_strobe;
> --
> 2.17.1
>
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