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Date:   Tue, 18 Apr 2023 09:09:12 +0900
From:   Damien Le Moal <dlemoal@...nel.org>
To:     Rick Wertenbroek <rick.wertenbroek@...il.com>,
        alberto.dassatti@...g-vd.ch
Cc:     xxm@...k-chips.com, Shawn Lin <shawn.lin@...k-chips.com>,
        Bjorn Helgaas <bhelgaas@...gle.com>,
        Lorenzo Pieralisi <lpieralisi@...nel.org>,
        Krzysztof WilczyƄski <kw@...ux.com>,
        Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Heiko Stuebner <heiko@...ech.de>,
        Brian Norris <briannorris@...omium.org>,
        Johan Jonker <jbx6244@...il.com>,
        Caleb Connolly <kc@...tmarketos.org>,
        Corentin Labbe <clabbe@...libre.com>,
        Judy Hsiao <judyhsiao@...omium.org>,
        Arnaud Ferraris <arnaud.ferraris@...labora.com>,
        Hugh Cole-Baker <sigmaris@...il.com>,
        linux-pci@...r.kernel.org, linux-rockchip@...ts.infradead.org,
        devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4 00/11] PCI: rockchip: Fix RK3399 PCIe endpoint
 controller driver

On 4/17/23 18:26, Rick Wertenbroek wrote:
> This is a series of patches that fixes the PCIe endpoint controller driver
> for the Rockchip RK3399 SoC. The driver was introduced in commit
> cf590b078391 ("PCI: rockchip: Add EP driver for Rockchip PCIe controller")
> The original driver had issues and would not allow for the RK3399 to
> operate in PCIe endpoint mode correctly. This patch series fixes that so
> that the PCIe core controller of the RK3399 SoC can now act as a PCIe
> endpoint. This is v4 of the patch series and addresses the comments received
> during the review of the v3 [1]. The changes to the v3 are minor and none of
> them change the logic of the driver.
> 
> Thank you in advance for reviewing this patch series and hopefully
> getting this merged. Having a functional PCIe endpoint controller
> driver for the RK3399 would allow to develop further PCIe endpoint
> functions through the Linux PCIe endpoint framework using this SoC.
> 
> [1] https://lore.kernel.org/linux-pci/20230404082426.3880812-1-rick.wertenbroek@gmail.com/
> 
> Summary of changes to V3 :
> 
> * Set the fields in the standard order in the dtsi and removed unnecessary
>   change in associated documentation, thanks to Krzysztof for pointing this out.
> * Added comment to explain how MSI-X capabilities advertisement was removed.
> * Changed Damien Le Moal <damien.lemoal@...nsource.wdc.com> address to his
>   kernel.org address Damien Le Moal <dlemoal@...nel.org> in tags.
> * [minor] Simplified code where a power of 2 was applied followed by a ilog2
>   operation.
> * [minor] Small code changes, replaced constant variable by macro, split
>   remaining long lines.

I retested this series, all good. So my Tested-by tag stands.

Lorenzo, Krzysztof, Bjorn,

Let's please get this series queued for 6.4 ASAP as otherwise the rockchip EP
controller is unusable.

Also please note that working with Rick off-list, we found out that more fixes
are in fact needed for the PCI address mapping (ATU programming) on top of this
series. But the problems detected are subtle and harder to trigger. The fixes
needed involve changes to the EPC core API so we are still working on the best
way to do that. We'll work on another series on top of this one for addressing
these issues.


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