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Message-ID: <sbb4cbejalo5dpq3zceizmiwwfcnqvnfijok636exkwuiampja@qzjljebk6pyy>
Date: Thu, 20 Apr 2023 23:55:03 +0200
From: Marijn Suijten <marijn.suijten@...ainline.org>
To: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
Cc: Rob Clark <robdclark@...il.com>,
Abhinav Kumar <quic_abhinavk@...cinc.com>,
Sean Paul <sean@...rly.run>, David Airlie <airlied@...il.com>,
Daniel Vetter <daniel@...ll.ch>,
Adam Skladowski <a39.skl@...il.com>,
Loic Poulain <loic.poulain@...aro.org>,
Bjorn Andersson <andersson@...nel.org>,
Kuogee Hsieh <quic_khsieh@...cinc.com>,
Robert Foss <rfoss@...nel.org>, Vinod Koul <vkoul@...nel.org>,
Rajesh Yadav <ryadav@...eaurora.org>,
Jeykumar Sankaran <jsanka@...eaurora.org>,
Neil Armstrong <neil.armstrong@...aro.org>,
Chandan Uddaraju <chandanu@...eaurora.org>,
~postmarketos/upstreaming@...ts.sr.ht,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@...ainline.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Martin Botka <martin.botka@...ainline.org>,
Jami Kettunen <jami.kettunen@...ainline.org>,
linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org,
freedreno@...ts.freedesktop.org, linux-kernel@...r.kernel.org,
Jordan Crouse <jordan@...micpenguin.net>,
Archit Taneja <architt@...eaurora.org>,
Sravanthi Kollukuduru <skolluku@...eaurora.org>
Subject: Re: [PATCH v2 14/17] drm/msm/dpu: Document and enable TEAR
interrupts on DSI interfaces
On 2023-04-20 04:11:29, Dmitry Baryshkov wrote:
> On 17/04/2023 23:21, Marijn Suijten wrote:
> > All SoCs since DPU 5.0.0 have the tear interrupt registers moved out of
> > the PINGPONG block and into the INTF block. Wire up these interrupts
> > and IRQ masks on all supported hardware.
> >
> > Signed-off-by: Marijn Suijten <marijn.suijten@...ainline.org>
> > ---
> > .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 12 ++++++----
> > .../drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 12 ++++++----
> > .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 12 ++++++----
> > .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 8 ++++---
> > .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 8 ++++---
> > .../drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 8 ++++---
> > .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 12 ++++++----
> > .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 6 +++--
> > .../drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 12 ++++++----
> > .../gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 12 ++++++----
> > .../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 12 ++++++----
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 15 ++++++++++++
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 6 +++--
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 27 ++++++++++++++++++++++
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 4 ++++
> > 15 files changed, 125 insertions(+), 41 deletions(-)
>
> If there is v3 for some reason, please split this into two patches:
> core/interrups and SoC catalog changes.
I think you want a v3 for the vsync_sel _active_ rename in dpu_hw_top,
all other patches are r-b'd if I scanned through it all correctly. I
can definitely accommodate to that.
- Marijn
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