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Message-ID: <CAKXuJqgeK1i8pi5Wujy3tJRRk-6yajJtoQvZjs=639Mbid=Q0Q@mail.gmail.com>
Date: Fri, 21 Apr 2023 11:59:35 -0500
From: Steev Klimaszewski <steev@...i.org>
To: Luca Weiss <luca.weiss@...rphone.com>
Cc: "David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>,
Paolo Abeni <pabeni@...hat.com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Balakrishna Godavarthi <bgodavar@...eaurora.org>,
Rocky Liao <rjliao@...eaurora.org>,
Marcel Holtmann <marcel@...tmann.org>,
Johan Hedberg <johan.hedberg@...il.com>,
Luiz Augusto von Dentz <luiz.dentz@...il.com>,
Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
~postmarketos/upstreaming@...ts.sr.ht, phone-devel@...r.kernel.org,
netdev@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-bluetooth@...r.kernel.org,
linux-arm-msm@...r.kernel.org
Subject: Re: [PATCH RFC 3/4] arm64: dts: qcom: sm6350: add uart1 node
On Fri, Apr 21, 2023 at 9:12 AM Luca Weiss <luca.weiss@...rphone.com> wrote:
>
> Add the node describing uart1 incl. opp table and pinctrl.
>
> Signed-off-by: Luca Weiss <luca.weiss@...rphone.com>
> ---
> arch/arm64/boot/dts/qcom/sm6350.dtsi | 63 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 63 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> index 18c4616848ce..16c5e9a6c98a 100644
> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> @@ -378,6 +378,25 @@ opp-2073600000 {
> };
> };
>
> + qup_opp_table: opp-table-qup {
> + compatible = "operating-points-v2";
> +
> + opp-75000000 {
> + opp-hz = /bits/ 64 <75000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-100000000 {
> + opp-hz = /bits/ 64 <100000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
> +
> + opp-128000000 {
> + opp-hz = /bits/ 64 <128000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + };
> + };
> +
> pmu {
> compatible = "arm,armv8-pmuv3";
> interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW>;
> @@ -741,6 +760,22 @@ i2c0: i2c@...000 {
> status = "disabled";
> };
>
> + uart1: serial@...000 {
> + compatible = "qcom,geni-uart";
> + reg = <0 0x00884000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>;
> + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&rpmhpd SM6350_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
> + <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>;
> + interconnect-names = "qup-core", "qup-config";
> + status = "disabled";
> + };
> +
> i2c2: i2c@...000 {
> compatible = "qcom,geni-i2c";
> reg = <0 0x00888000 0 0x4000>;
> @@ -1726,6 +1761,34 @@ qup_i2c10_default: qup-i2c10-default-state {
> drive-strength = <2>;
> bias-pull-up;
> };
> +
> + qup_uart1_cts: qup-uart1-cts-default-state {
> + pins = "gpio61";
> + function = "qup01";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +
> + qup_uart1_rts: qup-uart1-rts-default-state {
> + pins = "gpio62";
> + function = "qup01";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + qup_uart1_tx: qup-uart1-tx-default-state {
> + pins = "gpio63";
> + function = "qup01";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
tx should come after the rx, this caught me too when I was doing my
bluetooth driver, it goes by name, not gpio#.
> + qup_uart1_rx: qup-uart1-rx-default-state {
> + pins = "gpio64";
> + function = "qup01";
> + drive-strength = <2>;
> + bias-disable;
> + };
> };
>
> apps_smmu: iommu@...00000 {
>
> --
> 2.40.0
>
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