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Message-ID: <m5areidrpevtl6kbdoaikrvaxhq2cttgzklncqq3uygrsduzuf@anfyqmxtge73>
Date:   Wed, 26 Apr 2023 11:37:41 +0200
From:   Andrew Jones <ajones@...tanamicro.com>
To:     Heiko Stuebner <heiko@...ech.de>
Cc:     palmer@...belt.com, linux-riscv@...ts.infradead.org,
        paul.walmsley@...ive.com, kito.cheng@...ive.com, jrtc27@...c27.com,
        conor.dooley@...rochip.com, matthias.bgg@...il.com,
        heinrich.schuchardt@...onical.com, greentime.hu@...ive.com,
        nick.knight@...ive.com, christoph.muellner@...ll.eu,
        philipp.tomsich@...ll.eu, richard.henderson@...aro.org,
        arnd@...db.de, linux-kernel@...r.kernel.org,
        Heiko Stuebner <heiko.stuebner@...ll.eu>
Subject: Re: [PATCH 2/4] RISC-V: don't parse dt isa string to get rv32/rv64

On Mon, Apr 24, 2023 at 09:49:09PM +0200, Heiko Stuebner wrote:
> From: Heiko Stuebner <heiko.stuebner@...ll.eu>
> 
> When filling hwcap the kernel already expects the isa string to start with
> rv32 if CONFIG_32BIT and rv64 if CONFIG_64BIT.
> 
> So when recreating the runtime isa-string we can also just go the other way
> to get the correct starting point for it.
> 
> Signed-off-by: Heiko Stuebner <heiko.stuebner@...ll.eu>
> ---
>  arch/riscv/kernel/cpu.c | 10 +++++++---
>  1 file changed, 7 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
> index ebc478f0a16c..06c2f587a176 100644
> --- a/arch/riscv/kernel/cpu.c
> +++ b/arch/riscv/kernel/cpu.c
> @@ -244,7 +244,7 @@ static void strcat_isa_ext(char *isa_str)
>   */
>  static const char base_riscv_exts[13] = "imafdqcbkjpvh";
>  
> -static char *riscv_create_isa_string(const char *isa)
> +static char *riscv_create_isa_string(void)
>  {
>  	int maxlen = 4;
>  	char *isa_str;
> @@ -261,7 +261,11 @@ static char *riscv_create_isa_string(const char *isa)
>  		return ERR_PTR(-ENOMEM);
>  
>  	/* Print the rv[64/32] part */
> -	strncat(isa_str, isa, 4);
> +#if IS_ENABLED(CONFIG_32BIT)
> +	strncat(isa_str, "rv32", 4);
> +#elif IS_ENABLED(CONFIG_64BIT)
> +	strncat(isa_str, "rv64", 4);
> +#endif

I see we do the validation in riscv_fill_hwcap() and we also do this
#ifdeffery there, but I can't see any reason not to do

 if (IS_ENABLED(CONFIG_32BIT))
    ...
 else
    ...

instead.


>  
>  	for (i = 0; i < sizeof(base_riscv_exts); i++) {
>  		if (__riscv_isa_extension_available(NULL, base_riscv_exts[i] - 'a'))
> @@ -280,7 +284,7 @@ static void print_isa(struct seq_file *f, const char *isa)
>  
>  	seq_puts(f, "isa\t\t: ");
>  
> -	isa_str = riscv_create_isa_string(isa);
> +	isa_str = riscv_create_isa_string();

Why are we still passing 'isa' to print_isa()? It's now unused and
print_isa()'s single caller only fetches it from the DT for this
one purpose, so that of_property_read_string() call could now also
be dropped.

>  	if (!IS_ERR(isa_str)) {
>  		seq_write(f, isa_str, strlen(isa_str));
>  		kfree(isa_str);
> -- 
> 2.39.0
>

Thanks,
drew

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