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Message-ID: <04f4e968-946e-cbf0-3d78-cfe6cb17afb3@motor-comm.com>
Date: Wed, 26 Apr 2023 17:59:54 +0800
From: Frank Sae <Frank.Sae@...or-comm.com>
To: Samin Guo <samin.guo@...rfivetech.com>,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
netdev@...r.kernel.org, Peter Geis <pgwipeout@...il.com>
Cc: "David S . Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>,
Paolo Abeni <pabeni@...hat.com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Andrew Lunn <andrew@...n.ch>,
Heiner Kallweit <hkallweit1@...il.com>,
Russell King <linux@...linux.org.uk>,
Yanhong Wang <yanhong.wang@...rfivetech.com>
Subject: Re: [PATCH v1 1/2] dt-bindings: net: motorcomm: Add pad driver
strength cfg
On 2023/4/26 14:35, Samin Guo wrote:
> The motorcomm phy (YT8531) supports the ability to adjust the drive
> strength of the rx_clk/rx_data, the value range of pad driver
> strength is 0 to 7.
>
> Signed-off-by: Samin Guo <samin.guo@...rfivetech.com>
> ---
> .../devicetree/bindings/net/motorcomm,yt8xxx.yaml | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/net/motorcomm,yt8xxx.yaml b/Documentation/devicetree/bindings/net/motorcomm,yt8xxx.yaml
> index 157e3bbcaf6f..e648e486b6d8 100644
> --- a/Documentation/devicetree/bindings/net/motorcomm,yt8xxx.yaml
> +++ b/Documentation/devicetree/bindings/net/motorcomm,yt8xxx.yaml
> @@ -18,6 +18,16 @@ properties:
> - ethernet-phy-id4f51.e91a
> - ethernet-phy-id4f51.e91b
>
> + rx-clk-driver-strength:
> + description: drive strength of rx_clk pad.
> + enum: [ 0, 1, 2, 3, 4, 5, 6, 7 ]
> + default: 3
> +
> + rx-data-driver-strength:
> + description: drive strength of rxd/rx_ctl rgmii pad.
> + enum: [ 0, 1, 2, 3, 4, 5, 6, 7 ]
> + default: 3
> +
rx-clk-driver-strength and rx-data-driver-strength are not standard, so please add "motorcomm,".
rx-clk-driver-strength => motorcomm,rx-clk-driver-strength
> rx-internal-delay-ps:
> description: |
> RGMII RX Clock Delay used only when PHY operates in RGMII mode with
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