linux-kernel - Re: [PATCH] net: phy: aquantia: Add 10mbps support

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <28a1b515-b5f8-45cf-b1af-1a1826cb45ba@lunn.ch>
Date:   Thu, 4 May 2023 14:24:35 +0200
From:   Andrew Lunn <andrew@...n.ch>
To:     "Vyas, Devang nayanbhai" <Devangnayanbhai.Vyas@....com>
Cc:     "hkallweit1@...il.com" <hkallweit1@...il.com>,
        "linux@...linux.org.uk" <linux@...linux.org.uk>,
        "davem@...emloft.net" <davem@...emloft.net>,
        "edumazet@...gle.com" <edumazet@...gle.com>,
        "pabeni@...hat.com" <pabeni@...hat.com>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Jakub Kicinski <kuba@...nel.org>
Subject: Re: [PATCH] net: phy: aquantia: Add 10mbps support

On Thu, May 04, 2023 at 06:18:11AM +0000, Vyas, Devang nayanbhai wrote:
> [AMD Official Use Only - General]

Hi Devang

Please don't top post.

Also, wrap your emails at around 75 characters. Network Etiquette
rules apply for linux kernel mailling list.

> We are using AQR113C Marvell PHY which is CL45 based and based on below check in phy_probe() function:
>         if (phydrv->features)
>                 linkmode_copy(phydev->supported, phydrv->features);
>         else if (phydrv->get_features)
>                 err = phydrv->get_features(phydev);
>         else if (phydev->is_c45)
>                 err = genphy_c45_pma_read_abilities(phydev);    -> it reads capability from PMA register where 10M bit is read-only static and value is 0
>         else
>                 err = genphy_read_abilities(phydev);
> 
> Based on PHY datasheet, it supports 10M and we have made the change for the same and verified successfully.
> 
> Below code should set the supported field under genphy_c45_pma_read_abilities(), but as the value is 0, we have to set the 10M mode explicitly.

So the PHY is 'broken' in that one of its registers has the wrong
value. However, it can probably be fixed. aQuantia firmware is not
just code executed by its embedded uC. It also contains
`provisioning`. This blob sets the values of many registers, and i
think can be used to set registers which are read only. Maybe the blob
you have is incorrectly provisioning the MDIO_PMA_EXTABLE_10BT
register.

Please talk to Marvell about the provisioning blob you have.

       Andrew