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Message-ID: <CAJF2gTSWgiQOidm5S-XqzfXff1HS+p=V4zUFD0mMBvUa-b0OFw@mail.gmail.com>
Date:   Mon, 8 May 2023 14:22:27 +0800
From:   Guo Ren <guoren@...nel.org>
To:     Jisheng Zhang <jszhang@...nel.org>, Wei Fu <wefu@...hat.com>,
        Wei Fu <tekkamanninja@...il.com>
Cc:     Thomas Gleixner <tglx@...utronix.de>,
        Marc Zyngier <maz@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Palmer Dabbelt <palmer@...belt.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
        linux-riscv@...ts.infradead.org
Subject: Re: [PATCH 5/5] MAINTAINERS: add entry for T-HEAD RISC-V SoC

On Mon, May 8, 2023 at 2:34 AM Jisheng Zhang <jszhang@...nel.org> wrote:
>
> I would like to temporarily maintain the T-HEAD RISC-V SoC support.
Wei Fu is working on TH1520, and maybe you could have a discussion
with him? Thx.

F.Y.I

Wei Fu <wefu@...hat.com>

>
> Signed-off-by: Jisheng Zhang <jszhang@...nel.org>
> ---
>  MAINTAINERS | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 7e0b87d5aa2e..e1e51accec4f 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -18155,6 +18155,12 @@ T:     git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
>  F:     Documentation/devicetree/bindings/riscv/
>  F:     arch/riscv/boot/dts/
>
> +RISC-V THEAD SoC SUPPORT
> +M:     Jisheng Zhang <jszhang@...nel.org>
> +L:     linux-riscv@...ts.infradead.org
> +S:     Maintained
> +F:     arch/riscv/boot/dts/thead/
> +
>  RNBD BLOCK DRIVERS
>  M:     Md. Haris Iqbal <haris.iqbal@...os.com>
>  M:     Jack Wang <jinpu.wang@...os.com>
> --
> 2.40.0
>


-- 
Best Regards
 Guo Ren

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