linux-kernel - Re: [PATCH 0/5] Add Sipeed Lichee Pi 4A RISC-V board support

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <CAJF2gTScma2OXQv-2ALkZuuVtJA-tAhhi9B4b0No4DNPkH7Ekw@mail.gmail.com>
Date:   Mon, 8 May 2023 14:16:49 +0800
From:   Guo Ren <guoren@...nel.org>
To:     Jisheng Zhang <jszhang@...nel.org>, Wei Fu <wefu@...hat.com>,
        Wei Fu <tekkamanninja@...il.com>
Cc:     Thomas Gleixner <tglx@...utronix.de>,
        Marc Zyngier <maz@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Palmer Dabbelt <palmer@...belt.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
        linux-riscv@...ts.infradead.org
Subject: Re: [PATCH 0/5] Add Sipeed Lichee Pi 4A RISC-V board support

F.Y.I Wei Fu <wefu@...hat.com>


On Mon, May 8, 2023 at 2:34 AM Jisheng Zhang <jszhang@...nel.org> wrote:
>
> Sipeed's Lichee Pi 4A development board uses Lichee Module 4A core
> module which is powered by T-HEAD's light(a.k.a TH1520) SoC. Add
> minimal device tree files for the core module and the development
> board.
>
> Support basic uart/gpio/dmac drivers, so supports booting to a basic
> shell.
>
> Jisheng Zhang (5):
>   irqchip/sifive-plic: Support T-HEAD's C910 PLIC
>   riscv: Add the T-HEAD SoC family Kconfig option
>   riscv: dts: add initial T-HEAD light SoC device tree
>   riscv: dts: thead: add sipeed Lichee Pi 4A board device tree
>   MAINTAINERS: add entry for T-HEAD RISC-V SoC
>
>  .../sifive,plic-1.0.0.yaml                    |   4 +
>  MAINTAINERS                                   |   6 +
>  arch/riscv/Kconfig.socs                       |   6 +
>  arch/riscv/boot/dts/Makefile                  |   1 +
>  arch/riscv/boot/dts/thead/Makefile            |   2 +
>  .../dts/thead/light-lichee-module-4a.dtsi     |  38 ++
>  .../boot/dts/thead/light-lichee-pi-4a.dts     |  32 ++
>  arch/riscv/boot/dts/thead/light.dtsi          | 454 ++++++++++++++++++
>  drivers/irqchip/irq-sifive-plic.c             |   1 +
>  9 files changed, 544 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/thead/Makefile
>  create mode 100644 arch/riscv/boot/dts/thead/light-lichee-module-4a.dtsi
>  create mode 100644 arch/riscv/boot/dts/thead/light-lichee-pi-4a.dts
>  create mode 100644 arch/riscv/boot/dts/thead/light.dtsi
>
> --
> 2.40.0
>


--
Best Regards
 Guo Ren