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Message-ID: <394696a52bf1d767044e3f990cebfbaf69dabe70.camel@icenowy.me>
Date: Mon, 08 May 2023 11:32:17 +0800
From: Icenowy Zheng <uwu@...nowy.me>
To: Conor Dooley <conor@...nel.org>, Jisheng Zhang <jszhang@...nel.org>
Cc: Thomas Gleixner <tglx@...utronix.de>,
Marc Zyngier <maz@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Albert Ou <aou@...s.berkeley.edu>,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
linux-riscv@...ts.infradead.org, Guo Ren <guoren@...nel.org>,
heiko@...ech.de
Subject: Re: [PATCH 3/5] riscv: dts: add initial T-HEAD light SoC device tree
在 2023-05-07星期日的 22:35 +0100,Conor Dooley写道:
> Hey Jisheng,
>
> On Mon, May 08, 2023 at 02:23:02AM +0800, Jisheng Zhang wrote:
>
> > + c910_0: cpu@0 {
> > + compatible = "thead,c910", "riscv";
> > + device_type = "cpu";
> > + riscv,isa = "rv64imafdc";
>
> Does this support more than "rv64imafdc"?
> I assume there's some _xtheadfoo extensions that it does support,
> although I am not sure how we are proceeding with those - Heiko might
> have a more nuanced take.
>
> > + reset: reset-sample {
> > + compatible = "thead,reset-sample";
>
> What is a "reset-sample"?
>
> > + entry-reg = <0xff 0xff019050>;
> > + entry-cnt = <4>;
> > + control-reg = <0xff 0xff015004>;
> > + control-val = <0x1c>;
> > + csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3
> > 0x7c5 0x7cc>;
> > + };
> > +
> > + plic: interrupt-controller@...8000000 {
> > + compatible = "thead,c910-plic";
> > + reg = <0xff 0xd8000000 0x0 0x01000000>;
> > + interrupts-extended = <&cpu0_intc 11>,
> > <&cpu0_intc 9>,
> > + <&cpu1_intc 11>,
> > <&cpu1_intc 9>,
> > + <&cpu2_intc 11>,
> > <&cpu2_intc 9>,
> > + <&cpu3_intc 11>,
> > <&cpu3_intc 9>;
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + riscv,ndev = <240>;
> > + };
> > +
> > + clint: timer@...c000000 {
> > + compatible = "thead,c900-clint";
>
> "c900"? That a typo or intentional. Hard to tell since this
> compatible
> is undocumented ;)
Intentional, for supporting both C906 and C910.
However, as we discussed in some binding patches, there should be a DT
binding string per chip.
So here should be "thead,light-clint", "thead,c900-clint".
(Or use th1520, the marketing name, instead of light, the codename)
P.S. which one is preferred by DT binding maintainers, the marketing
name or the codename?
>
> > + reg = <0xff 0xdc000000 0x0 0x00010000>;
> > + interrupts-extended = <&cpu0_intc 3>,
> > <&cpu0_intc 7>,
> > + <&cpu1_intc 3>,
> > <&cpu1_intc 7>,
> > + <&cpu2_intc 3>,
> > <&cpu2_intc 7>,
> > + <&cpu3_intc 3>,
> > <&cpu3_intc 7>;
> > + };
> > +
> > + uart0: serial@...7014000 {
> > + compatible = "snps,dw-apb-uart";
> > + reg = <0xff 0xe7014000 0x0 0x4000>;
> > + interrupts = <36>;
> > + clocks = <&uart_sclk>;
> > + clock-names = "baudclk";
>
> dtbs_check complains about this clock name.
> > +
> > + dmac0: dmac@...fc00000 {
>
> dma-controller@
>
> As I mentioned in the other patch, please clean up the dtbs_check
> complaints for v2.
>
> Cheers,
> Conor.
>
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