linux-kernel - Re: Need suggestions for smp related properties in cpus.yaml to support smpboot for cortex-r52 based platform

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Message-ID: <d8544d01-b0a0-f5f6-b0fe-8f6c25bed9bb@linaro.org>
Date:   Thu, 11 May 2023 19:17:39 +0200
From:   Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To:     Ayan Kumar Halder <ayankuma@....com>, robh+dt@...nel.org,
        krzysztof.kozlowski+dt@...aro.org, matthias.bgg@...il.com,
        angelogioacchino.delregno@...labora.com, geert+renesas@...der.be,
        magnus.damm@...il.com, konrad.dybcio@...aro.org,
        andersson@...nel.org, mazziesaccount@...il.com,
        conor.dooley@...rochip.com, j@...nau.net, mailingradian@...il.com,
        me@...ren.info, lpieralisi@...nel.org
Cc:     devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org,
        linux-mediatek@...ts.infradead.org,
        linux-renesas-soc@...r.kernel.org, Julien Grall <julien@....org>,
        Stefano Stabellini <sstabellini@...nel.org>,
        Michal Orzel <michal.orzel@....com>,
        Michal Simek <michal.simek@...inx.com>
Subject: Re: Need suggestions for smp related properties in cpus.yaml to
 support smpboot for cortex-r52 based platform

On 11/05/2023 11:35, Ayan Kumar Halder wrote:
> Hi Device Tree engineers,
> 
> 
> Recently I have ported Xen on Cortex-R52 (AArch32-V8R processor) for our 
> AMD platform.
> 
> I was discussing with xen-devel community about how we can properly 
> support smpboot when I was suggested that this might be the correct 
> forum for discussion.
> 
> Please refer 
> https://lists.xenproject.org/archives/html/xen-devel/2023-05/msg00224.html 
> and the follow-ups for context.
> 
> 
> The way smpboot works on our platform is as follows:-
> 
> 1. core0 writes to register (say regA) the address of the secondary core 
> initialization routine.
> 
> 2. core0 writes to another register (say regB) the value "0x1" to put 
> the secondary core in reset mode.
> 
> 3. core0 writes to regB the value "0x0" to pull the secondary core out 
> of reset mode.
> 
> regA, regB will differ for core1, core2, core3 and so on.
> 
> 
> Currently, I am trying to bringup core1 only.
> 
> 
> I am thinking to use "enable-method=spin-table" in the cpu node for 
> core1.  So that I can use "cpu-release-address" for regA.
> 
> For regB, I am thinking of introducing a new property 
> "amd-cpu-reset-addr" in the cpu node.

Propose a patch, that's how we discuss. Anyway as this is arm then you
have a machine for your platform right? The address is not fixed?

If the the regb is not a pen release-like, so you cannot use
secondary-boot-reg, then check how other machines are doing it.

Best regards,
Krzysztof