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Message-ID: <ZF6UWBd0x9LxAhoJ@bhelgaas>
Date: Fri, 12 May 2023 14:32:40 -0500
From: Bjorn Helgaas <helgaas@...nel.org>
To: Thippeswamy Havalige <thippeswamy.havalige@....com>
Cc: linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, krzysztof.kozlowski@...aro.org,
bhelgaas@...gle.com, michals@...inx.com, robh+dt@...nel.org,
nagaradhesh.yeleswarapu@....com, bharat.kumar.gogada@....com,
lorenzo.pieralisi@....com
Subject: Re: [PATCH v2 3/3] PCI: xilinx-xdma: Add Xilinx XDMA Root Port driver
On Fri, May 12, 2023 at 11:57:25AM +0530, Thippeswamy Havalige wrote:
> Add support for Xilinx XDMA Soft IP core as Root Port.
> ...
> +#include <linux/of_pci.h>
> +#include <linux/irqchip/chained_irq.h>
The trend seems to be to alphabetize the system includes above.
> +#include "pcie-xilinx-common.h"
> +
> +#include "../pci.h"
Put the pcie-xilinx-common.h include here, as you did for
pcie-xilinx-cpm.c:
#include <linux/irqchip/chained_irq.h>
#include "../pci.h"
#include "pcie-xilinx-common.h"
pcie-xilinx.c has a very similar list of register definitions, which
makes me wonder why it can't share pcie-xilinx-common.h as well.
Obviously it would take a bit of rework since it uses BIT(x) instead
of just "x". But you hide the "BIT()" inside IMR(), which is arguably
slightly obscure since the #define value is not a register mask:
> +#define IMR(x) BIT(XILINX_PCIE_INTR_ ##x)
I don't really care either way, but it seems like a possibly needless
difference.
Bjorn
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