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Message-ID: <67944796-cdc8-77a8-d99f-16eeff865923@starfivetech.com>
Date: Fri, 12 May 2023 15:25:53 +0800
From: Xingyu Wu <xingyu.wu@...rfivetech.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
Conor Dooley <conor@...nel.org>
CC: <linux-riscv@...ts.infradead.org>, <devicetree@...r.kernel.org>,
"Michael Turquette" <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
"Philipp Zabel" <p.zabel@...gutronix.de>,
Emil Renner Berthing <kernel@...il.dk>,
"Rob Herring" <robh+dt@...nel.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
"Hal Feng" <hal.feng@...rfivetech.com>,
William Qiu <william.qiu@...rfivetech.com>,
<linux-kernel@...r.kernel.org>, <linux-clk@...r.kernel.org>
Subject: Re: [PATCH v4 7/7] riscv: dts: starfive: jh7110: Add PLL clock node
and modify syscrg node
On 2023/5/12 15:22, Krzysztof Kozlowski wrote:
> On 12/05/2023 09:15, Xingyu Wu wrote:
>> On 2023/5/12 14:37, Krzysztof Kozlowski wrote:
>>> On 12/05/2023 04:20, Xingyu Wu wrote:
>>>> Add the PLL clock node for the Starfive JH7110 SoC and
>>>> modify the SYSCRG node to add PLL clocks input.
>>>
>>>
>>>> @@ -465,6 +469,12 @@ syscrg: clock-controller@...20000 {
>>>> sys_syscon: syscon@...30000 {
>>>> compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd";
>>>> reg = <0x0 0x13030000 0x0 0x1000>;
>>>> +
>>>> + pllclk: clock-controller {
>>>> + compatible = "starfive,jh7110-pll";
>>>> + clocks = <&osc>;
>>>> + #clock-cells = <1>;
>>>
>>> This should be part of previous patch. You just added that node. Don't
>>> add half of devices but entire device.
>>>
>>
>> So do I merge the patch 6 and patch 7 into one patch and add syscon and
>> clock-controller together?
>
> I am okay with adding users of clocks in separate patch, but the clock
> controller - so part of SYS - should be added when adding SYS.
>
Got it. Thanks.
Best regards,
Xingyu Wu
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