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Message-ID: <20230515210545.2100161-1-gnstark@sberdevices.ru>
Date: Tue, 16 May 2023 00:05:45 +0300
From: George Stark <gnstark@...rdevices.ru>
To: <jic23@...nel.org>, <lars@...afoo.de>, <neil.armstrong@...aro.org>,
<khilman@...libre.com>, <jbrunet@...libre.com>,
<martin.blumenstingl@...glemail.com>, <andy.shevchenko@...il.com>,
<nuno.sa@...log.com>
CC: <linux-iio@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-amlogic@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>, <kernel@...rdevices.ru>,
<GNStark@...rdevices.ru>
Subject: [PATCH v1] meson saradc: fix clock divider mask length
From: George Stark <GNStark@...rdevices.ru>
According to datasheets of supported meson SOCs
length of ADC_CLK_DIV field is 6 bits long
Fixes: 3adbf3427330 ("iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs")
Signed-off-by: George Stark <GNStark@...rdevices.ru>
---
drivers/iio/adc/meson_saradc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
index 85b6826cc10c..b93ff42b8c19 100644
--- a/drivers/iio/adc/meson_saradc.c
+++ b/drivers/iio/adc/meson_saradc.c
@@ -72,7 +72,7 @@
#define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
#define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
#define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
- #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
+ #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 6
#define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
#define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
--
2.38.4
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