linux-kernel - Re: [PATCH v1] meson saradc: fix clock divider mask length

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <23cb7112-ce2e-cee6-2213-60fd599c998d@linaro.org>
Date:   Tue, 16 May 2023 10:22:33 +0200
From:   neil.armstrong@...aro.org
To:     George Stark <gnstark@...rdevices.ru>, jic23@...nel.org,
        lars@...afoo.de, khilman@...libre.com, jbrunet@...libre.com,
        martin.blumenstingl@...glemail.com, andy.shevchenko@...il.com,
        nuno.sa@...log.com
Cc:     linux-iio@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-amlogic@...ts.infradead.org, linux-kernel@...r.kernel.org,
        kernel@...rdevices.ru
Subject: Re: [PATCH v1] meson saradc: fix clock divider mask length

On 15/05/2023 23:05, George Stark wrote:
> From: George Stark <GNStark@...rdevices.ru>
> 
> According to datasheets of supported meson SOCs
> length of ADC_CLK_DIV field is 6 bits long
> 
> Fixes: 3adbf3427330 ("iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs")
> Signed-off-by: George Stark <GNStark@...rdevices.ru>
> ---
>   drivers/iio/adc/meson_saradc.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
> index 85b6826cc10c..b93ff42b8c19 100644
> --- a/drivers/iio/adc/meson_saradc.c
> +++ b/drivers/iio/adc/meson_saradc.c
> @@ -72,7 +72,7 @@
>   	#define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK	GENMASK(20, 18)
>   	#define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK	GENMASK(17, 16)
>   	#define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT		10
> -	#define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH		5
> +	#define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH		6
>   	#define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK		GENMASK(9, 8)
>   	#define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK		GENMASK(7, 0)
>   

Reviewed-by: Neil Armstrong <neil.armstrong@...aro.org>