linux-kernel - RE: [PATCH v2 1/1] vfio/nvgpu: Add vfio pci variant module for grace hopper

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Message-ID: <BN9PR11MB52763B1BC1C88EB8C24E2AD88C7E9@BN9PR11MB5276.namprd11.prod.outlook.com>
Date:   Wed, 17 May 2023 07:29:09 +0000
From:   "Tian, Kevin" <kevin.tian@...el.com>
To:     "ankita@...dia.com" <ankita@...dia.com>,
        "jgg@...dia.com" <jgg@...dia.com>,
        "alex.williamson@...hat.com" <alex.williamson@...hat.com>
CC:     "aniketa@...dia.com" <aniketa@...dia.com>,
        "cjia@...dia.com" <cjia@...dia.com>,
        "kwankhede@...dia.com" <kwankhede@...dia.com>,
        "targupta@...dia.com" <targupta@...dia.com>,
        "vsethi@...dia.com" <vsethi@...dia.com>,
        "Currid, Andy" <acurrid@...dia.com>,
        "apopple@...dia.com" <apopple@...dia.com>,
        "jhubbard@...dia.com" <jhubbard@...dia.com>,
        "danw@...dia.com" <danw@...dia.com>,
        "kvm@...r.kernel.org" <kvm@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH v2 1/1] vfio/nvgpu: Add vfio pci variant module for grace
 hopper

> From: ankita@...dia.com <ankita@...dia.com>
> Sent: Tuesday, May 9, 2023 12:08 PM
> 
> From: Ankit Agrawal <ankita@...dia.com>
> 
> NVIDIA's upcoming Grace Hopper Superchip provides a PCI-like device
> for the on-chip GPU that is the logical OS representation of the
> internal propritary cache coherent interconnect.
> 
> This representation has a number of limitations compared to a real PCI
> device, in particular, it does not model the coherent GPU memory
> aperture as a PCI config space BAR, and PCI doesn't know anything
> about cacheable memory types.
> 
> Provide a VFIO PCI variant driver that adapts the unique PCI
> representation into a more standard PCI representation facing
> userspace. The GPU memory aperture is obtained from ACPI using
> device_property_read_u64(), according to the FW specification,
> and exported to userspace as the VFIO_REGION that covers the first
> PCI BAR. qemu will naturally generate a PCI device in the VM where the
> cacheable aperture is reported in BAR1.

BAR2.

and it's more informative by describing how many BARs this device
already implements then BAR2 is selected because it's free.

> +
> +static int nvgpu_vfio_pci_open_device(struct vfio_device *core_vdev)
> +{
> +	struct vfio_pci_core_device *vdev =
> +		container_of(core_vdev, struct vfio_pci_core_device, vdev);
> +	int ret;
> +
> +	ret = vfio_pci_core_enable(vdev);
> +	if (ret)
> +		return ret;
> +
> +	vfio_pci_core_finish_enable(vdev);
> +
> +	return ret;
> +}

NIT. "return 0" as other variant drivers do.


> +
> +MODULE_LICENSE("GPL v2");
> +MODULE_AUTHOR("Ankit Agrawal <ankita@...dia.com>");
> +MODULE_AUTHOR("Aniket Agashe <aniketa@...dia.com>");
> +MODULE_DESCRIPTION(
> +	"VFIO NVGPU PF - User Level driver for NVIDIA devices with CPU
> coherently accessible device memory");

what does 'PF' mean? Physical function?

Probably needs a more specific name for the coherent part... nvgpu-vfio-pci
sounds covering all NV GPUs.