linux-kernel - Re: [PATCH v1] meson saradc: fix clock divider mask length

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Date:   Wed, 17 May 2023 12:21:00 +0300
From:   Dmitry Rokosov <ddrokosov@...rdevices.ru>
To:     Martin Blumenstingl <martin.blumenstingl@...glemail.com>
CC:     George Stark <gnstark@...rdevices.ru>, <jic23@...nel.org>,
        <lars@...afoo.de>, <neil.armstrong@...aro.org>,
        <khilman@...libre.com>, <jbrunet@...libre.com>,
        <andy.shevchenko@...il.com>, <nuno.sa@...log.com>,
        <linux-iio@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-amlogic@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>, <kernel@...rdevices.ru>
Subject: Re: [PATCH v1] meson saradc: fix clock divider mask length

Hello Martin,

On Tue, May 16, 2023 at 09:08:26PM +0200, Martin Blumenstingl wrote:
> Hi George,
> 
> thank you for this patch!
> 
> On Mon, May 15, 2023 at 11:06 PM George Stark <gnstark@...rdevices.ru> wrote:
> >
> > From: George Stark <GNStark@...rdevices.ru>
> >
> > According to datasheets of supported meson SOCs
> > length of ADC_CLK_DIV field is 6 bits long
> I have a question about this sentence which doesn't affect this patch
> - it's only about managing expectations:
> Which SoC are you referring to?
> This divider is only relevant on older SoCs that predate GXBB (S905).
> To my knowledge all SoCs from GXBB onwards place the divider in the
> main or AO clock controller, so this bitmask is irrelevant there.
> 

We are currently working with the A1 SoC family, specifically the A113L
variant. According to the datasheet for the A113L, the ADC_CLK_DIV can
be found in the SAR_ADC_REG3 register as a 6-bit value located within
bits 15 through 10.

> > Fixes: 3adbf3427330 ("iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs")
> > Signed-off-by: George Stark <GNStark@...rdevices.ru>
> Since my question above doesn't affect this patch:
> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@...glemail.com>

-- 
Thank you,
Dmitry