linux-kernel - Re: [PATCH v1] meson saradc: fix clock divider mask length

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Date:   Wed, 17 May 2023 14:37:37 +0300
From:   Vyacheslav <adeep@...ina.in>
To:     Martin Blumenstingl <martin.blumenstingl@...glemail.com>,
        George Stark <gnstark@...rdevices.ru>
Cc:     jic23@...nel.org, lars@...afoo.de, neil.armstrong@...aro.org,
        khilman@...libre.com, jbrunet@...libre.com,
        andy.shevchenko@...il.com, nuno.sa@...log.com,
        linux-iio@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-amlogic@...ts.infradead.org, linux-kernel@...r.kernel.org,
        kernel@...rdevices.ru
Subject: Re: [PATCH v1] meson saradc: fix clock divider mask length

Hi, Martin,

On 16.05.2023 22:08, Martin Blumenstingl wrote:
> Hi George,
> 
> thank you for this patch!
> 
> On Mon, May 15, 2023 at 11:06 PM George Stark <gnstark@...rdevices.ru> wrote:
>>
>> From: George Stark <GNStark@...rdevices.ru>
>>
>> According to datasheets of supported meson SOCs
>> length of ADC_CLK_DIV field is 6 bits long
> I have a question about this sentence which doesn't affect this patch
> - it's only about managing expectations:
> Which SoC are you referring to?

I checked the 905x, 905x3, a113x datasheets - there is the same register 
with 6 bits for  ADC_CLK_DIV

> This divider is only relevant on older SoCs that predate GXBB (S905).
> To my knowledge all SoCs from GXBB onwards place the divider in the
> main or AO clock controller, so this bitmask is irrelevant there.
> 
>> Fixes: 3adbf3427330 ("iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs")
>> Signed-off-by: George Stark <GNStark@...rdevices.ru>
> Since my question above doesn't affect this patch:
> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@...glemail.com>
> 
> _______________________________________________
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> linux-amlogic@...ts.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-amlogic

-- 
Vyacheslav Bocharov

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