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Message-ID: <20230518-unharmed-stencil-2a18bbdd3651@spud>
Date: Thu, 18 May 2023 21:57:55 +0100
From: Conor Dooley <conor@...nel.org>
To: Jisheng Zhang <jszhang@...nel.org>
Cc: Thomas Gleixner <tglx@...utronix.de>,
Marc Zyngier <maz@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Albert Ou <aou@...s.berkeley.edu>, Guo Ren <guoren@...nel.org>,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
linux-riscv@...ts.infradead.org, Yangtao Li <frank.li@...o.com>,
Wei Fu <wefu@...hat.com>, Icenowy Zheng <uwu@...nowy.me>
Subject: Re: [PATCH v2 8/9] MAINTAINERS: add entry for T-HEAD RISC-V SoC
On Fri, May 19, 2023 at 02:45:40AM +0800, Jisheng Zhang wrote:
> Currently, I would like to maintain the T-HEAD RISC-V SoC support.
>
> Signed-off-by: Jisheng Zhang <jszhang@...nel.org>
Acked-by: Conor Dooley <conor.dooley@...rochip.com>
Thanks,
Conor.
> ---
> MAINTAINERS | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index e0ad886d3163..6df20c65798a 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -18162,6 +18162,12 @@ F: drivers/perf/riscv_pmu.c
> F: drivers/perf/riscv_pmu_legacy.c
> F: drivers/perf/riscv_pmu_sbi.c
>
> +RISC-V THEAD SoC SUPPORT
> +M: Jisheng Zhang <jszhang@...nel.org>
> +L: linux-riscv@...ts.infradead.org
> +S: Maintained
> +F: arch/riscv/boot/dts/thead/
> +
> RNBD BLOCK DRIVERS
> M: Md. Haris Iqbal <haris.iqbal@...os.com>
> M: Jack Wang <jinpu.wang@...os.com>
> --
> 2.40.0
>
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