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Message-ID: <20230518-slider-pointless-14c1e653cc1c@spud>
Date: Thu, 18 May 2023 22:02:05 +0100
From: Conor Dooley <conor@...nel.org>
To: Jisheng Zhang <jszhang@...nel.org>
Cc: Thomas Gleixner <tglx@...utronix.de>,
Marc Zyngier <maz@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Albert Ou <aou@...s.berkeley.edu>, Guo Ren <guoren@...nel.org>,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
linux-riscv@...ts.infradead.org, Yangtao Li <frank.li@...o.com>,
Wei Fu <wefu@...hat.com>, Icenowy Zheng <uwu@...nowy.me>
Subject: Re: [PATCH v2 6/9] riscv: dts: add initial T-HEAD TH1520 SoC device
tree
On Fri, May 19, 2023 at 02:45:38AM +0800, Jisheng Zhang wrote:
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&c910_0>;
> + };
> +
> + core1 {
> + cpu = <&c910_1>;
> + };
> +
> + core2 {
> + cpu = <&c910_2>;
> + };
> +
> + core3 {
> + cpu = <&c910_3>;
> + };
> + };
> + };
We actually don't need to add these anymore, I fixed our topology
detection :) No harm to keep it though!
> + cpurst: cpurst {
> + compatible = "thead,reset-th1520";
> + entry-reg = <0xff 0xff019050>;
> + entry-cnt = <4>;
> + control-reg = <0xff 0xff015004>;
> + control-val = <0x1c>;
> + csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;
> + };
I figure this will be no surprise to you:
arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dtb: soc: cpurst: {'compatible': ['thead,reset-th1520'], 'entry-reg': [[1099494953040]], 'entry-cnt': [[4]], 'control-reg': [[255, 4278276100]], 'control-val': [[28]], 'csr-copy': [[2035, 1984, 1985, 1986, 1987, 1989, 1996]]} should not be valid under {'type': 'object'}
arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dtb: cpurst: control-reg:0: [255, 4278276100] is too long
> + dmac0: dma-controller@...fc00000 {
> + compatible = "snps,axi-dma-1.01a";
> + reg = <0xff 0xefc00000 0x0 0x1000>;
> + interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&apb_clk>, <&apb_clk>;
> + clock-names = "core-clk", "cfgr-clk";
> + #dma-cells = <1>;
> + dma-channels = <4>;
> + snps,block-size = <65536 65536 65536 65536>;
> + snps,priority = <0 1 2 3>;
> + snps,dma-masters = <1>;
> + snps,data-width = <4>;
> + snps,axi-max-burst-len = <16>;
> + status = "disabled";
^^^^^^^^^^^^^^^^^^^^^^^
These are spaces :(
> + };
Cheers,
Conor.
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