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Message-ID: <56ac76e8-e5ac-3712-1e07-ad6c5b96c77c@quicinc.com>
Date:   Fri, 19 May 2023 15:00:43 -0700
From:   Abhinav Kumar <quic_abhinavk@...cinc.com>
To:     Konrad Dybcio <konrad.dybcio@...aro.org>,
        Rob Clark <robdclark@...il.com>,
        Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
        Sean Paul <sean@...rly.run>, David Airlie <airlied@...il.com>,
        Daniel Vetter <daniel@...ll.ch>,
        "Kalyan Thota" <quic_kalyant@...cinc.com>,
        Shubhashree Dhar <dhar@...eaurora.org>,
        Raviteja Tamatam <travitej@...eaurora.org>,
        Krishna Manikandan <quic_mkrishn@...cinc.com>
CC:     Rob Clark <robdclark@...omium.org>,
        <linux-arm-msm@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <dri-devel@...ts.freedesktop.org>,
        "Marijn Suijten" <marijn.suijten@...ainline.org>,
        <freedreno@...ts.freedesktop.org>
Subject: Re: [PATCH v2] drm/msm/dpu: Set DPU_DATA_HCTL_EN for in
 INTF_SC7180_MASK



On 5/19/2023 11:49 AM, Konrad Dybcio wrote:
> DPU5 and newer targets enable this unconditionally. Move it from the
> SC7280 mask to the SC7180 one.
> 

You mean DPU 5.0.0 right?

> Fixes: 7e6ee55320f0 ("drm/msm/disp/dpu1: enable DATA_HCTL_EN for sc7280 target")
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
> Reviewed-by: Marijn Suijten <marijn.suijten@...ainline.org>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@...aro.org>
> ---

I have cross-checked all the chipsets affected by this and confirmed 
DATA_HCTL is present and those 3 registers programmed with that feature 
bit are valid, hence

Reviewed-by: Abhinav Kumar <quic_abhinavk@...cinc.com>

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