lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Fri, 19 May 2023 15:21:41 -0700
From:   "Chang S. Bae" <chang.seok.bae@...el.com>
To:     Adamos Ttofari <attofari@...zon.de>, <tglx@...utronix.de>
CC:     <abusse@...zon.de>, Ingo Molnar <mingo@...hat.com>,
        Borislav Petkov <bp@...en8.de>,
        Dave Hansen <dave.hansen@...ux.intel.com>, <x86@...nel.org>,
        "H. Peter Anvin" <hpa@...or.com>, Kyle Huey <me@...ehuey.com>,
        Andrew Cooper <andrew.cooper3@...rix.com>,
        <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v3] x86: fpu: Keep xfd_state always in sync with
 MSR_IA32_XFD

On 5/19/2023 4:23 AM, Adamos Ttofari wrote:
> Commit 672365477ae8 ("x86/fpu: Update XFD state where required") and
> commit 8bf26758ca96 ("x86/fpu: Add XFD state to fpstate") introduced a
> per CPU variable xfd_state to keep the MSR_IA32_XFD value cached. In
> order to avoid unnecessary writes to the MSR.
> 
> On CPU hotplug MSR_IA32_XFD is reset to the init_fpstate.xfd, which
> wipes out any stale state. But the per CPU cached xfd value is not
> reset, which brings them out of sync.
> 
> As a consequence a subsequent xfd_update_state() might fail to update
> the MSR which in turn can result in XRSTOR raising a #NM in kernel
> space, which crashes the kernel.
> 
> To address the issue mentioned, initialize xfd_state together with
> MSR_IA32_XFD.
> 
> Fixes: 672365477ae8 ("x86/fpu: Update XFD state where required")
> 
> Signed-off-by: Adamos Ttofari <attofari@...zon.de>

Tested-by: Chang S. Bae <chang.seok.bae@...el.com>

With this test -- which I may follow up to be included the AMX selftest:
https://lore.kernel.org/lkml/6ab71997-8533-1828-7c62-717e2821f147@intel.com/

Thanks,
Chang

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ