linux-kernel - Re: [PATCH v4] mips: add <asm-generic/io.h> including

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Message-ID: <alpine.DEB.2.21.2305201531101.27887@angie.orcam.me.uk>
Date:   Sat, 20 May 2023 15:45:47 +0100 (BST)
From:   "Maciej W. Rozycki" <macro@...am.me.uk>
To:     Arnd Bergmann <arnd@...db.de>
cc:     Jiaxun Yang <jiaxun.yang@...goat.com>, linux-mips@...r.kernel.org,
        linux-kernel@...r.kernel.org,
        Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
        Linux-Arch <linux-arch@...r.kernel.org>,
        Baoquan He <bhe@...hat.com>,
        Huacai Chen <chenhuacai@...nel.org>
Subject: Re: [PATCH v4] mips: add <asm-generic/io.h> including

On Fri, 19 May 2023, Arnd Bergmann wrote:

> On most other architectures, we also don't define __raw_readq()
> and __raw_writeq() on 32-bit because they lose the atomicity that
> might be required for FIFO accesses, but the existing MIPS version
> has them, so changing those should be a separate patch after it
> can be shown to not break anything.

 With MIPS we have:

	if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
		*__mem = __val;						\
	else if (cpu_has_64bits) {					\
		unsigned long __flags;					\
		type __tmp;						\
									\
		if (irq)						\
			local_irq_save(__flags);			\
		__asm__ __volatile__(					\
			".set	push"		"\t\t# __writeq""\n\t"	\
			".set	arch=r4000"			"\n\t"	\
			"dsll32 %L0, %L0, 0"			"\n\t"	\
			"dsrl32 %L0, %L0, 0"			"\n\t"	\
			"dsll32 %M0, %M0, 0"			"\n\t"	\
			"or	%L0, %L0, %M0"			"\n\t"	\
			"sd	%L0, %2"			"\n\t"	\
			".set	pop"				"\n"	\
			: "=r" (__tmp)					\
			: "0" (__val), "m" (*__mem));			\
		if (irq)						\
			local_irq_restore(__flags);			\
	} else								\
		BUG();							\

etc. so we don't actually lose atomicity, because we always use 64-bit 
operations (SD above, store-doubleword) and we BUG if they are not there 
(i.e. with 32-bit hardware; not a build-time check as in principle the 
same 32-bit kernel image ought to run just fine both on 32-bit and 64-bit 
hardware).  A few MIPS platforms do use them, e.g. SB1250, which requires 
64-bit unswapped accesses to SoC registers.

  Maciej