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Message-ID: <dde2e4b5ac6018adb9bfae05bb3800af6b7c0f0e.1684767562.git.michal.simek@amd.com>
Date:   Mon, 22 May 2023 16:59:52 +0200
From:   Michal Simek <michal.simek@....com>
To:     <linux-kernel@...r.kernel.org>, <monstr@...str.eu>,
        <michal.simek@...inx.com>, <git@...inx.com>
CC:     Radhey Shyam Pandey <radhey.shyam.pandey@....com>,
        Conor Dooley <conor+dt@...nel.org>,
        Harini Katakam <harini.katakam@....com>,
        "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@...aro.org>,
        Laurent Pinchart <laurent.pinchart@...asonboard.com>,
        Michael Grzeschik <m.grzeschik@...gutronix.de>,
        Rob Herring <robh+dt@...nel.org>,
        "Robert Hancock" <robert.hancock@...ian.com>,
        Tanmay Shah <tanmay.shah@....com>,
        <devicetree@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>
Subject: [PATCH v2 5/6] arm64: zynqmp: Add pmu interrupt-affinity

From: Radhey Shyam Pandey <radhey.shyam.pandey@....com>

Based on dt-binding "This property should present when there is more than a
single SPI" that's also case that's why explicitly specify interrupt
affinity to avoid incorrect usage.

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@....com>
Signed-off-by: Michal Simek <michal.simek@....com>
---

Changes in v2:
- Update commit message to remove OS content - reported by Laurent

This avoids the following error upon linux boot:
armv8-pmu pmu: hw perfevents: no interrupt-affinity property,
guessing.

---
 arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index 02bd75900238..fc5e21bc647c 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -164,6 +164,10 @@ pmu {
 			     <0 144 4>,
 			     <0 145 4>,
 			     <0 146 4>;
+		interrupt-affinity = <&cpu0>,
+				     <&cpu1>,
+				     <&cpu2>,
+				     <&cpu3>;
 	};
 
 	psci {
-- 
2.36.1

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