linux-kernel - [PATCH v2 4/6] arm64: zynqmp: Add L2 cache nodes

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Message-ID: <d962547cd72286821714b45f52b0126f9c438919.1684767562.git.michal.simek@amd.com>
Date:   Mon, 22 May 2023 16:59:51 +0200
From:   Michal Simek <michal.simek@....com>
To:     <linux-kernel@...r.kernel.org>, <monstr@...str.eu>,
        <michal.simek@...inx.com>, <git@...inx.com>
CC:     Radhey Shyam Pandey <radhey.shyam.pandey@....com>,
        Conor Dooley <conor+dt@...nel.org>,
        Harini Katakam <harini.katakam@....com>,
        "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@...aro.org>,
        Laurent Pinchart <laurent.pinchart@...asonboard.com>,
        Piyush Mehta <piyush.mehta@...inx.com>,
        Rob Herring <robh+dt@...nel.org>,
        Robert Hancock <robert.hancock@...ian.com>,
        Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@...inx.com>,
        Tanmay Shah <tanmay.shah@....com>,
        <devicetree@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>
Subject: [PATCH v2 4/6] arm64: zynqmp: Add L2 cache nodes

From: Radhey Shyam Pandey <radhey.shyam.pandey@....com>

Describe SoC L2 cache hierarchy.

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@....com>
Signed-off-by: Michal Simek <michal.simek@....com>
---

Changes in v2:
- Update commit message to remove Linux part - reported by Laurent

Linux kernel throws "cacheinfo: Unable to detect cache hierarchy for
CPU 0" warning when booting on zu+ Soc. To fix it add the L2 cache
node and let each CPU point to it.

---
 arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index a961bb6f31ff..02bd75900238 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -33,6 +33,7 @@ cpu0: cpu@0 {
 			operating-points-v2 = <&cpu_opp_table>;
 			reg = <0x0>;
 			cpu-idle-states = <&CPU_SLEEP_0>;
+			next-level-cache = <&L2>;
 		};
 
 		cpu1: cpu@1 {
@@ -42,6 +43,7 @@ cpu1: cpu@1 {
 			reg = <0x1>;
 			operating-points-v2 = <&cpu_opp_table>;
 			cpu-idle-states = <&CPU_SLEEP_0>;
+			next-level-cache = <&L2>;
 		};
 
 		cpu2: cpu@2 {
@@ -51,6 +53,7 @@ cpu2: cpu@2 {
 			reg = <0x2>;
 			operating-points-v2 = <&cpu_opp_table>;
 			cpu-idle-states = <&CPU_SLEEP_0>;
+			next-level-cache = <&L2>;
 		};
 
 		cpu3: cpu@3 {
@@ -60,6 +63,12 @@ cpu3: cpu@3 {
 			reg = <0x3>;
 			operating-points-v2 = <&cpu_opp_table>;
 			cpu-idle-states = <&CPU_SLEEP_0>;
+			next-level-cache = <&L2>;
+		};
+
+		L2: l2-cache {
+			compatible = "cache";
+			cache-level = <2>;
 		};
 
 		idle-states {
-- 
2.36.1