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Message-ID: <ZG/VgDIbmEg7IiDe@linux.dev>
Date: Thu, 25 May 2023 21:39:12 +0000
From: Oliver Upton <oliver.upton@...ux.dev>
To: Mark Brown <broonie@...nel.org>
Cc: Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will@...nel.org>, Marc Zyngier <maz@...nel.org>,
James Morse <james.morse@....com>,
Suzuki K Poulose <suzuki.poulose@....com>,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
kvmarm@...ts.linux.dev, Shaoqin Huang <shahuang@...hat.com>
Subject: Re: [PATCH v2 2/7] arm64/sysreg: Convert MDSCR_EL1 to automatic
register generation
On Tue, May 23, 2023 at 07:37:00PM +0100, Mark Brown wrote:
> Convert MDSCR_EL1 to automatic register generation as per DDI0616 2023-03.
> No functional change.
>
> Reviewed-by: Shaoqin Huang <shahuang@...hat.com>
> Signed-off-by: Mark Brown <broonie@...nel.org>
> ---
> arch/arm64/include/asm/sysreg.h | 1 -
> arch/arm64/tools/sysreg | 28 ++++++++++++++++++++++++++++
> 2 files changed, 28 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 3d69bda0e608..95de1aaee0e9 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -135,7 +135,6 @@
> #define SYS_SVCR_SMSTOP_SMZA_EL0 sys_reg(0, 3, 4, 6, 3)
>
> #define SYS_OSDTRRX_EL1 sys_reg(2, 0, 0, 0, 2)
> -#define SYS_MDSCR_EL1 sys_reg(2, 0, 0, 2, 2)
> #define SYS_OSDTRTX_EL1 sys_reg(2, 0, 0, 3, 2)
> #define SYS_OSECCR_EL1 sys_reg(2, 0, 0, 6, 2)
> #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4)
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index df7a7ba97b43..601cc8024734 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -55,6 +55,34 @@ Field 29 TX
> Res0 28:0
> EndSysreg
>
> +Sysreg MDSCR_EL1 2 0 0 2 2
> +Res0 63:36
> +Field 35 EHBWE
> +Field 34 EnSPM
> +Field 33 TTA
> +Field 32 EMBWE
> +Field 31 TFO
> +Field 30 RXfull
> +Field 29 TXfull
> +Res0 28
> +Field 27 RXO
> +Field 26 TXU
> +Res0 25:24
> +Field 23:22 INTdis
> +Field 21 TDA
> +Res0 20
> +Field 19 SC2
> +Res0 18:16
These bits are actually RAZ/WI. I know that doesn't amount to much right
now, but eventually getting a mask of RAZ/WI bits for registers would be
helpful for KVM sysreg emulation.
> +Field 15 MDE
> +Field 14 HDE
> +Field 13 KDE
> +Field 12 TDCC
> +Res0 11:7
> +Field 6 ERR
> +Res0 5:1
> +Field 0 SS
> +EndSysreg
> +
> Sysreg ID_PFR0_EL1 3 0 0 1 0
> Res0 63:32
> UnsignedEnum 31:28 RAS
>
> --
> 2.30.2
>
--
Thanks,
Oliver
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