linux-kernel - Re: [PATCH v2 1/2] dt-bindings: clock: mediatek: replace unusable clock

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Message-ID: <f3f7df94-74f1-dd41-00d7-0ab4fa2e4d61@collabora.com>
Date:   Fri, 26 May 2023 10:30:14 +0200
From:   AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@...labora.com>
To:     Alexandre Mergnat <amergnat@...libre.com>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Matthias Brugger <matthias.bgg@...il.com>,
        Chen-Yu Tsai <wenst@...omium.org>
Cc:     Markus Schneider-Pargmann <msp@...libre.com>,
        linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-mediatek@...ts.infradead.org
Subject: Re: [PATCH v2 1/2] dt-bindings: clock: mediatek: replace unusable
 clock

Il 25/05/23 16:50, Alexandre Mergnat ha scritto:
> The “mcu_pm_bclk_ck_cg” clock is used by co-processors and should not be
> added to the kernel driver, otherwise the CPU just halt and the board is
> rebooted by the wathdog.
> 
> Instead, add the "aes_top0_bclk_ck_cg" missing clock to prevent
> re-shuffling index and then preserve the ABI.

It's still a breakage. Besides, have you tried to add it as CLK_IS_CRITICAL? :-)

Cheers,
Angelo

> 
> Signed-off-by: Alexandre Mergnat <amergnat@...libre.com>
> ---
>   include/dt-bindings/clock/mediatek,mt8365-clk.h | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/include/dt-bindings/clock/mediatek,mt8365-clk.h b/include/dt-bindings/clock/mediatek,mt8365-clk.h
> index f9aff1775810..0a841e7cc1c3 100644
> --- a/include/dt-bindings/clock/mediatek,mt8365-clk.h
> +++ b/include/dt-bindings/clock/mediatek,mt8365-clk.h
> @@ -199,7 +199,7 @@
>   #define CLK_IFR_PWRAP_TMR		46
>   #define CLK_IFR_PWRAP_SPI		47
>   #define CLK_IFR_PWRAP_SYS		48
> -#define CLK_IFR_MCU_PM_BK		49
> +#define CLK_IFR_AES_TOP0_BK		49
>   #define CLK_IFR_IRRX_26M		50
>   #define CLK_IFR_IRRX_32K		51
>   #define CLK_IFR_I2C0_AXI		52
>