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Message-ID: <fecc9d6a-022e-49d9-a452-8a63c409ebf3@sirena.org.uk>
Date: Fri, 26 May 2023 16:36:15 +0100
From: Mark Brown <broonie@...nel.org>
To: William Qiu <william.qiu@...rfivetech.com>
Cc: devicetree@...r.kernel.org, linux-spi@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Emil Renner Berthing <kernel@...il.dk>,
Ziv Xu <ziv.xu@...rfivetech.com>
Subject: Re: [PATCH v1 2/3] spi: cadence-quadspi: Add clock configuration for
StarFive JH7110 QSPI
On Fri, May 26, 2023 at 02:25:28PM +0800, William Qiu wrote:
> if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) {
> + qspi_ahb = devm_clk_get(dev, "qspi-ahb");
> + if (IS_ERR(qspi_ahb)) {
> + dev_err(dev, "Cannot claim QSPI_AHB clock.\n");
> + ret = PTR_ERR(qspi_ahb);
> + return ret;
> + }
> +
> + ret = clk_prepare_enable(qspi_ahb);
> + if (ret) {
> + dev_err(dev, "Cannot enable QSPI AHB clock.\n");
> + goto probe_clk_failed;
> + }
Nothing ever disables or unprepares this clock as far as I can tell?
Perhaps also consider using the clk_bulk_ APIs.
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