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Message-ID: <7hsfbjxcqs.fsf@baylibre.com>
Date: Fri, 26 May 2023 09:45:47 -0700
From: Kevin Hilman <khilman@...nel.org>
To: Markus Schneider-Pargmann <msp@...libre.com>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>
Cc: linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org,
Alexandre Mergnat <amergnat@...libre.com>
Subject: Re: [PATCH] clk: mediatek: mt8365: Fix inverted topclk operations
Markus Schneider-Pargmann <msp@...libre.com> writes:
> just wanted to ask if I need to do something specific for it to go into
> a rc? Sorry if I missed doing something for that, I haven't had to fix
> something in an rc that often before.
I think the Fixes tag is enough to indicate that.
Steven, is there still time for this fix be queued up for v6.4-rc?
Thanks,
Kevin
> On Thu, May 11, 2023 at 03:32:26PM +0200, Markus Schneider-Pargmann wrote:
>> The given operations are inverted for the wrong registers which makes
>> multiple of the mt8365 hardware units unusable. In my setup at least usb
>> did not work.
>>
>> Fixed by swapping the operations with the inverted ones.
>>
>> Reported-by: Alexandre Mergnat <amergnat@...libre.com>
>> Fixes: 905b7430d3cc ("clk: mediatek: mt8365: Convert simple_gate to mtk_gate clocks")
>> Signed-off-by: Markus Schneider-Pargmann <msp@...libre.com>
>> ---
>> drivers/clk/mediatek/clk-mt8365.c | 6 +++---
>> 1 file changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-mt8365.c
>> index 6b4e193f648d..6d785ec5754d 100644
>> --- a/drivers/clk/mediatek/clk-mt8365.c
>> +++ b/drivers/clk/mediatek/clk-mt8365.c
>> @@ -583,15 +583,15 @@ static const struct mtk_gate_regs top2_cg_regs = {
>>
>> #define GATE_TOP0(_id, _name, _parent, _shift) \
>> GATE_MTK(_id, _name, _parent, &top0_cg_regs, \
>> - _shift, &mtk_clk_gate_ops_no_setclr_inv)
>> + _shift, &mtk_clk_gate_ops_no_setclr)
>>
>> #define GATE_TOP1(_id, _name, _parent, _shift) \
>> GATE_MTK(_id, _name, _parent, &top1_cg_regs, \
>> - _shift, &mtk_clk_gate_ops_no_setclr)
>> + _shift, &mtk_clk_gate_ops_no_setclr_inv)
>>
>> #define GATE_TOP2(_id, _name, _parent, _shift) \
>> GATE_MTK(_id, _name, _parent, &top2_cg_regs, \
>> - _shift, &mtk_clk_gate_ops_no_setclr)
>> + _shift, &mtk_clk_gate_ops_no_setclr_inv)
>>
>> static const struct mtk_gate top_clk_gates[] = {
>> GATE_TOP0(CLK_TOP_CONN_32K, "conn_32k", "clk32k", 10),
>> --
>> 2.40.1
>>
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